The week's pick
Random Articles
Reseach Article
VLSI Implementation of Heterogeneous Adder for Performance Optimization
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 7 |
| Year of Publication: 2012 |
| Authors: Raminder Preet Pal Singh, Ashish Chaturvedi |
10.5120/8057-1405
|
Raminder Preet Pal Singh, Ashish Chaturvedi . VLSI Implementation of Heterogeneous Adder for Performance Optimization. International Journal of Computer Applications. 51, 7 ( August 2012), 37-40. DOI=10.5120/8057-1405
Abstract
An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always in larger area occupied by circuit on chip and vice-versa. In order to design an optimized adder circuit which provides area/delay tradeoffs, we studied different available parallel, synchronous adders and proposed a new adder based on combination of them. In this paper, we proposed a new type of adder architecture known as heterogeneous adder that consists of concatenation of sub-adder (homogeneous adder) of different types. The heterogeneous adder architecture provides better design tradeoffs in terms of area and delay characteristics.
References
- B. Parhami, 2000, Computer Arithmetic, Algorithm and Hardware Design, Oxford University Press, New York, pp. 91-119.
- Pong P. Chu "RTL Hardware Design Using VHDL: coding for Efficiency, Portability and Scalability" Wiley-IEEE Press, New Jercy, 2006
- Hasan Krad and Aws Yousif Al-Taie, "Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL", Journal of Computer Science 4 (2008): 305-308.
- Asadi, P. and K. Navi "A novel high-speed 54-54-bit multiplier", Am. J. Applied Sci. , 4 (9) (2007): 666-672.
- Z. Abid, H. El-Razouk and D. A. El-Dib, "Low power multipliers based on new hybrid full adders", Microelectronics Journal, Volume 39, Issue 12, 2008, 1509-1515.
- Nagendra, C. ; Irwin, M. J. ; Owens, R. M. ,"Area-time-power tradeoffs in parallel adders", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 43, Issue 10, (1996): 689 – 702.
- Wang, Y. ; Pai, C. ; Song, X. , "The design of hybrid carry look-ahead/carry-select adders, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 49, Issue 1, (Jan 2002) : 16-24.
- May Phyo Thwal, Khin Htay Kyi, and Kyaw Swar Soe, "Implementation of Adder-Subtracter design with VerilogHDL", International Journal of Electronics, Circuits and Systems Volume 2 number 3, 2008.
- Min Cha and Earl E. Swartzlander, Jr, "Modified Carry Skip Adder for reducing first block delay", Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing MI, 2000: 346-348.
- Yu Shen Lin, "Delay Efficient 32-bit Carry-Skip Adder", Electronics, Circuits and Systems, 2006, ICECS '06, pp. 506-509.
- Behnam Amelifard, Farzan Fallah, Massoud Pedram, "Closing the gap between Carry Select Adder and Ripple Carry Adder: A new class of Low-power and High-performance Adders", Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED'05) , 2005.
- Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang, "A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability", 0-7803-8834-8/05/$20 ?2005 IEEE, 2005.
- Pak K. Chan, et al, Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming, IEEE Transactions on Computers, vol. 41, No. 8 (Aug. 1992): 920-93.
- Sarabdeep Singh and dilip Kumar, "Design of Area and Power Efficient Modified Carry Select Adder", International Journal of Computer Application (November 2011), vol. 33 – No. 3.
Index Terms
Keywords