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The Performance and Analysis of an Efficient Model of DC to DC Converter for on Chip Circuitry using a Less Number of Power Devices
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 9 |
| Year of Publication: 2012 |
| Authors: K. Arutselvan, C. Manoharan, T. Balaji |
10.5120/8072-1467
|
K. Arutselvan, C. Manoharan, T. Balaji . The Performance and Analysis of an Efficient Model of DC to DC Converter for on Chip Circuitry using a Less Number of Power Devices. International Journal of Computer Applications. 51, 9 ( August 2012), 33-39. DOI=10.5120/8072-1467
Abstract
This paper presents an efficient DC to DC converter for on chip circuitry which gives high-energy conversion quality using CMOS Driver-Receiver Pair for Low-Swing Signaling. The efficiency has increased due to the use of power FETs, which are able to switch at high frequency more efficiently than power bipolar transistors, which incur more switching losses and require a more complicated drive circuit. The proposed schemes perform better than the other schemes in terms of power consumption, delay, and energy delay product. Moreover, the proposed scheme requires no reference voltages, and multiple threshold voltage processes. In addition the other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This proposed work also takes care of the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.
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