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An Efficient Design of Vedic Multiplier using new Encoding Scheme
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 53 - Number 11 |
| Year of Publication: 2012 |
| Authors: Jai Skand Tripathi, Priya Keerti Tripathi, Deepti Shakti Tripathi |
10.5120/8463-2346
|
Jai Skand Tripathi, Priya Keerti Tripathi, Deepti Shakti Tripathi . An Efficient Design of Vedic Multiplier using new Encoding Scheme. International Journal of Computer Applications. 53, 11 ( September 2012), 6-10. DOI=10.5120/8463-2346
Abstract
This paper presents a design of efficient Digital Vedic Multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If we are looking towards the signal processing, we will find multipliers and adders plays a very important roll. In fact if we make our focus we can see speed of the Digital signal processing systems is mainly dependent on multipliers and adders. A processor requires more hardware and processing time during multiplication rather than addition and subtraction. In this paper we proposed a new digital Vedic multiplier structure based on a new encoding algorithm. We found that this algorithm reduces the number of partial products so reduces the adders. Thus multiplier is going to faster. In this paper we use Xilinx VHDL module for simulation of Encoder.
References
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