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Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs

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International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 53 - Number 13
Year of Publication: 2012
Authors:
Jamuna. S
V. K. Agrawal
10.5120/8481-2421

Jamuna. S and V K Agrawal. Article: Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs. International Journal of Computer Applications 53(13):18-22, September 2012. Full text available. BibTeX

@article{key:article,
	author = {Jamuna. S and V. K. Agrawal},
	title = {Article: Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {53},
	number = {13},
	pages = {18-22},
	month = {September},
	note = {Full text available}
}

Abstract

Field programmable gate arrays (FPGAs) are the reconfigurable logic devices which are widely used in many applications like system prototyping, complex computing systems, automotive electronics and mobile devices. FPGAs have become very popular at present because of their features like high logic capacity, reconfigurability and regular structure with less area cost. However, increase in density and complexity also has resulted in more probability of defects. FPGAs are prone to different types of faults similar to other complicated integrated circuit chips. Faults may occur due to many reasons like environmental conditions or aging of the device. The rate of occurrence of permanent faults can be quite high in emerging technologies, and hence there is a need for periodic testing of such FPGAs. To effectively deal with the increased defect density, we need efficient methods for fault detection and correction. Here, we present an approach for testing FPGA interconnect that exploits the reprogramability of an FPGA to create built-in self test (BIST) logic by configuring it only during off-line testing. In this way, testability is achieved without any area overhead, since the BIST logic "disappears" when the circuit is reconfigured for its normal system operation. We have used XILINX ISE12. 1 for simulation and synthesis.

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