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Reseach Article

High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication

by D. Jayanthi, M. Rajaram
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 55 - Number 17
Year of Publication: 2012
Authors: D. Jayanthi, M. Rajaram
10.5120/8850-3131

D. Jayanthi, M. Rajaram . High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication. International Journal of Computer Applications. 55, 17 ( October 2012), 44-51. DOI=10.5120/8850-3131

@article{ 10.5120/8850-3131,
author = { D. Jayanthi, M. Rajaram },
title = { High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication },
journal = { International Journal of Computer Applications },
issue_date = { October 2012 },
volume = { 55 },
number = { 17 },
month = { October },
year = { 2012 },
issn = { 0975-8887 },
pages = { 44-51 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume55/number17/8850-3131/ },
doi = { 10.5120/8850-3131 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:57:32.796442+05:30
%A D. Jayanthi
%A M. Rajaram
%T High Performance Asynchronous Pipelined QDI Templates for DCT Matrix-vector Multiplication
%J International Journal of Computer Applications
%@ 0975-8887
%V 55
%N 17
%P 44-51
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The mass application of asynchronous design has been an elusive goal for academic researchers while recent advances are promising. However asynchronous circuit has some inherent advantages over synchronous counterpart. The matrix – vector multiplication core of discrete cosine transforms (DCT) is demonstrated in this paper, by non linear pipelined templates. From this proposed DCT applications, Quasi-Delay Insensitive (QDI) templates are introduced to yielding average high performance and low power. Novel control circuit templates have been used to simplify the design of such non linear pipelines. QDI circuits are quite robust in terms of process variations and design tolerances. Our proposed asynchronous design yields 35% higher average throughput and negligible energy overhead compared with conventional synchronous design.

References
  1. D. M. Chapiro, Globally-Asynchronous,Locally-Synchronous Systems, Ph. D. dissertation, Stanford Univ. , Stanford, CA, 1984, Stanford CS Tech. Rep. STAN-CS-84-1026.
  2. LARS S. NIELSEN AND JENS SPARSO, Designing Asynchronous Circuits for Low Power:An IFIR Filter Bank for a Digital Hearing Aid, proceedings of the ieee, vol. 87, no. 2, February 1999.
  3. J. Cortadella et al. , Logic Synthesis of Asynchronous Controllers and Interfaces. New York:Springer-Verlag, 2002.
  4. K. Rao and P. Yip, Discrete Cosine Transform, Algorithm, Advantages, Applications. New York: Academic, 1990.
  5. A. Madisetti and A. W. Jr, "A 100 MHz 2-D DCT/IDCT processor for HDTV applications," IEEE Trans. Circuits Syst. Video Technol. , vol. 5, no. 2, pp. 158–165, Apr. 1995.
  6. S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, M. Terane, and M. Yoshimoto, "A 100 MHz 2-D discrete cosine transform core processor," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 492–499, Apr. 1992.
  7. T. Xanthopoulos and A. P. Chandrakasan, "A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 693–703, May 1999.
  8. R. Manohar, "Width-adaptive data word architectures," in Adv. Res. VLSI, 2001, pp. 112–129.
  9. R. Canal, A. Gonzalez, and J. Smith, "Very low power pipelines using significance compression," in Proc. MICRO'33, Dec. 2000, pp. 181–190 .
  10. L. S. Nielsen and J. Sparsø, "Designing asynchronous circuits for lowpower: An IFIR filter bank for a digital hearing aid," Proc. IEEE, vol. 87, pp. 268–281, Feb. 1999.
  11. K. Kim, P. A. Beerel, and Y. Hong, "An asynchronous matrix–vector multiplier for discrete cosine transform," in Int. Symp. Low Power Electronics Design, Jul. 2000, pp. 256–261.
  12. LaFrieda, C. and R. Manohar, 2009. Reducing power consumption with relaxed quasi delay-insensitive circuits. Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, May 17- 20, IEEE Xplore Press, Washington, USA, pp: 217-226. DOI: 10. 1109/ASYNC. 2009. 9.
  13. AlainJ. Martin ,Asynchronous Techniques for System-on-Chip Design, Vol. 0018- 9219_2006. IEEE 94, No. 6, June 2006 , Proceedings of the IEEE.
  14. R. Manohar, "Width-adaptive data word architectures," in Adv. Res. VLSI, 2001, pp. 112–129.
  15. J. Teifel, D. Fang, D. Biermann, C. Kelly, and R. Manohar, "Energy-efficient pipelines," in Proc. Int. Symp. Advanced Research Asynchronous Circuits Systems, Apr. 2002, pp. 23–33.
Index Terms

Computer Science
Information Sciences

Keywords

Asynchronous channels control circuit templates discrete cosine transforms matrix vector multiplication Pre-Charged Full Buffer Reduced Stack Pre-Charged Half Buffer