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Design and Optimization of n-bit Reversible Binary Comparator

International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 55 - Number 18
Year of Publication: 2012
Rangaraju H G
Vinayak Hegde
Raja K B
Muralidhara K N

Rangaraju H G, Vinayak Hegde, Raja K B and Muralidhara K N. Article: Design and Optimization of n-bit Reversible Binary Comparator. International Journal of Computer Applications 55(18):22-30, October 2012. Full text available. BibTeX

	author = {Rangaraju H G and Vinayak Hegde and Raja K B and Muralidhara K N},
	title = {Article: Design and Optimization of n-bit Reversible Binary Comparator},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {55},
	number = {18},
	pages = {22-30},
	month = {October},
	note = {Full text available}


Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is designed using circuit for MSB as first stage to compare MSBs and one-bit comparator cell as second stage and so on to compare lesser significant bit positions. The power consumption, delay, garbage outputs and constant inputs are computed. It is observed that the quantum cost and garbage output values are less in the proposed technique compared to the existing approaches.


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