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Reseach Article

Design and Optimization of n-bit Reversible Binary Comparator

by Rangaraju H G, Vinayak Hegde, Raja K B, Muralidhara K N
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 55 - Number 18
Year of Publication: 2012
Authors: Rangaraju H G, Vinayak Hegde, Raja K B, Muralidhara K N
10.5120/8992-3072

Rangaraju H G, Vinayak Hegde, Raja K B, Muralidhara K N . Design and Optimization of n-bit Reversible Binary Comparator. International Journal of Computer Applications. 55, 18 ( October 2012), 22-30. DOI=10.5120/8992-3072

@article{ 10.5120/8992-3072,
author = { Rangaraju H G, Vinayak Hegde, Raja K B, Muralidhara K N },
title = { Design and Optimization of n-bit Reversible Binary Comparator },
journal = { International Journal of Computer Applications },
issue_date = { October 2012 },
volume = { 55 },
number = { 18 },
month = { October },
year = { 2012 },
issn = { 0975-8887 },
pages = { 22-30 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume55/number18/8992-3072/ },
doi = { 10.5120/8992-3072 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:57:36.695505+05:30
%A Rangaraju H G
%A Vinayak Hegde
%A Raja K B
%A Muralidhara K N
%T Design and Optimization of n-bit Reversible Binary Comparator
%J International Journal of Computer Applications
%@ 0975-8887
%V 55
%N 18
%P 22-30
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible logic has attracted significance attention in recent years, leading to different approaches such as synthesis, optimization, simulation and verification. In this paper, we propose the design and optimization of n-bit reversible binary comparator. The circuit for MSB and one-bit comparator cell using NOT, PG and CNOT gates are designed. The n-bit reversible binary comparator is designed using circuit for MSB as first stage to compare MSBs and one-bit comparator cell as second stage and so on to compare lesser significant bit positions. The power consumption, delay, garbage outputs and constant inputs are computed. It is observed that the quantum cost and garbage output values are less in the proposed technique compared to the existing approaches.

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Index Terms

Computer Science
Information Sciences

Keywords

Reversible Binary Comparator Quantum Cost Reversible Logic Garbage Output Constant Input.