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Design and Implementation of a Floating Point ALU on a STRATIX-III FPGA

International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 55 - Number 2
Year of Publication: 2012
Prashanth B. U. V
C. Padmini
S. Rajendar

Prashanth B U V, C Padmini and S Rajendar. Article: Design and Implementation of a Floating Point ALU on a STRATIX-III FPGA. International Journal of Computer Applications 55(2):48-50, October 2012. Full text available. BibTeX

	author = {Prashanth B. U. V and C. Padmini and S. Rajendar},
	title = {Article: Design and Implementation of a Floating Point ALU on a STRATIX-III FPGA},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {55},
	number = {2},
	pages = {48-50},
	month = {October},
	note = {Full text available}


In this paper, the implementation of DSP modules such as a floating point ALU are presented and designed. The design is based on high performance FPGA "STRATIX III". The implementation is done after functional and timing simulation. The simulation tool used is Model Sim. The tool for synthesis and implementation is QuartusII [2]. The experimental results shows the functional and timing analysis for the fixed point to floating converter DSP module carried out using high performance synthesis software from Altera[1]. One of the most important stages of fixed-point to floating-point conversion is the evaluation of the floating-point specification accuracy. This evaluation is required to optimize the data word-length according to accuracy constraints. Classical methods for accuracy evaluation are based on floating-point simulations but they lead to very long optimization times. The use of this method in data word-length minimization processes reduces significantly the optimization time.


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