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Leakage Power Reduction in CMOS VLSI Circuits

International Journal of Computer Applications
© 2012 by IJCA Journal
Volume 55 - Number 8
Year of Publication: 2012
Pushpa Saini
Rajesh Mehra

Pushpa Saini and Rajesh Mehra. Article: Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Computer Applications 55(8):42-48, October 2012. Full text available. BibTeX

	author = {Pushpa Saini and Rajesh Mehra},
	title = {Article: Leakage Power Reduction in CMOS VLSI Circuits},
	journal = {International Journal of Computer Applications},
	year = {2012},
	volume = {55},
	number = {8},
	pages = {42-48},
	month = {October},
	note = {Full text available}


Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth, stacking transistors etc. In this paper, new methods have been proposed for the leakage power reduction in 90nm technology. The proposed methods will be compared with the previous existing leakage reduction techniques. The result is simulated using Microwind 3. 1 in 90nm CMOS technology at room temperature.


  • Jae Woong Chun and C. Y. Roger Chen, "A Novel Leakage Power Reduction Technique for CMOS Circuit Design", International Conference on SoC Design Conference (ISOCC), pp. 119-122 , IEEE 2010
  • Tezaswi Raja, Vishwani D. Agrawal and Michael L. Bushnell "Variable Input Delay CMOS Logic for Low Power Design", IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 17, Issue: 10, pp. 1534-1545, 2009
  • Sarvesh Bhardwaj and Sarma Vrudhula, "Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, Issue: 3, pp. 445-455, March 2008.
  • Anup K. Sultania, Dennis Sylvester, and Sachin S. Sapatnekar, "Gate Oxide Leakage and Delay Tradeoffs for Dual-Tox Circuits", IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 13, Issue: 12, pp. 1362-1375, December 2005.
  • Yuanlin Lu and Vishwani D. Agrawal "CMOS Leakage and Glitch Minimization for Power Performance Tradeoff" IEEE Journal of Low Power Electronics, Vol. 2, pp. 1-10, 2006.
  • M. S. Islam, M. Sultana Nasrin, Nuzhat Mansur and Naila Tasneem, "Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design", 6th International Conference on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, pp. 18-20, IEEE December 2010.
  • Ashoka Santhanur, Luca Benini, "Row–Based Power– Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits", IEEE Transactions on VLSI Systems, Vol. 19, Issue: 3, pp. 469-482, March 2011.
  • Fallah, F. , and Pedram, M. - Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits. IEICE Transactions on Electronics, Special Section on Low-Power LSI and Low-Power IP E88-C, 4 (April 2005), 509-519.
  • Salendra. Govindarajulu, "Low Power, Reduced Dynamic Voltage Swing Domino Logic Circuits" Indian Journal of Computer Science and Engineering, Vol. 1, No. 2, pp. 74-81.
  • Jun Cheol Park, Vincent J. Mooney III, and Philipp Pfeiffenberger , "Sleepy Stack Reduction of Leakage Power", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,Vol. 14, No. 11, pp. 1250–1263, 2006.
  • S. G. Narendra and A. P. Chandrakasan, Leakage in Nanometer CMOS Technologies. Berlin, Germany: Springer-Verlag, 2006, pp. 21–40.
  • K. K. Kim and Y. -B. Kim, "A novel adaptive design methodology for minimum leakage power considering PVT variations on nanoscale VLSI systems," IEEE Trans. Very Large Scale Integration (VLSI), Vol. 17, No. 4, pp. 517–528, Apr. 2009.
  • Heung Jun Jeon, Yong-Bin Kim, and Minsu Choi, "Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems", IEEE Transactions on Instrumentation and Measurement, Vol. 59, No. 5, pp. 1127-1133, May 2010.
  • Shuzhe Zhou, Hailong Yao, Qiang Zhou, "Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment", IEEE Computer Society Annual Symposium on VLSI, pp. 212-217, 2011.
  • Philippe Matherat, Mariem Slimani "Multiple Threshold Voltage for Glitch Power Reduction", Faible Tension Faible Consommation (FTFC), pp. 67-70, IEEE 2011.
  • Se Hun Kim, Vincent J. Mooney III, "Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design", 2006 IFIP International Conference on Very Large Scale Integration, Oct. 2006, pp. 367 – 372.