The week's pick
Random Articles
Reseach Article
Trade-offs in designing High-Performance Digital Adder based on Heterogeneous Architecture
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 56 - Number 13 |
| Year of Publication: 2012 |
| Authors: Raminder Preet Pal Singh, Ashish Chaturvedi, Onkar Singh |
10.5120/8950-3132
|
Raminder Preet Pal Singh, Ashish Chaturvedi, Onkar Singh . Trade-offs in designing High-Performance Digital Adder based on Heterogeneous Architecture. International Journal of Computer Applications. 56, 13 ( October 2012), 12-16. DOI=10.5120/8950-3132
Abstract
To design an efficient integrated circuit in terms of Area, Power and speed is one of the challenging task in modern VLSI design field. In the past decade numbers of research have been carried out to optimize design based on area, speed and power utilization. In this paper performance analysis of different available adder architectures has been carried out and then we proposed a Heterogeneous architecture, which composed of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder unit in order to demonstrate trade-offs between performance parameters i. e. Area, Power and speed. We consider area optimization under delay constraint, area optimization under power constraint and finally power optimization under delay constraint. All the adders are design using VHDL. To get power, delay and area report, we use XILINX 9. 1 i as synthesis tool and Modelsim XE III 6. 2g for simulation. FPGA-Spartan III is used for implementation.
References
- B. Parhami, 2000, Computer Arithmetic, Algorithm and Hardware Design, Oxford University Press, New York, pp. 91-119.
- Pong P. Chu "RTL Hardware Design Using VHDL: coding for Efficiency, Portability and Scalability" Wiley-IEEE Press, New Jercy, 2006
- Hasan Krad and Aws Yousif Al-Taie, "Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL", Journal of Computer Science 4 (2008): 305-308.
- Asadi, P. and K. Navi "A novel high-speed 54-54-bit multiplier", Am. J. Applied Sci. , 4 (9) (2007): 666-672.
- Z. Abid, H. El-Razouk and D. A. El-Dib, "Low power multipliers based on new hybrid full adders", Microelectronics Journal, Volume 39, Issue 12, 2008, 1509-1515.
- Nagendra, C. ; Irwin, M. J. ; Owens, R. M. ,"Area-time-power tradeoffs in parallel adders", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 43, Issue 10, (1996): 689 – 702.
- Wang, Y. ; Pai, C. ; Song, X. , "The design of hybrid carry look-ahead/carry-select adders, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on Volume 49, Issue 1, (Jan 2002) : 16-24.
- May Phyo Thwal, Khin Htay Kyi, and Kyaw Swar Soe, "Implementation of Adder-Subtracter design with VerilogHDL", International Journal of Electronics, Circuits and Systems Volume 2 number 3, 2008.
- Min Cha and Earl E. Swartzlander, Jr, "Modified Carry Skip Adder for reducing first block delay", Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing MI, 2000: 346-348.
- Yu Shen Lin, "Delay Efficient 32-bit Carry-Skip Adder", Electronics, Circuits and Systems, 2006, ICECS '06, pp. 506-509.
- Behnam Amelifard, Farzan Fallah, Massoud Pedram, "Closing the gap between Carry Select Adder and Ripple Carry Adder: A new class of Low-power and High-performance Adders", Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED'05) , 2005.
- Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang, "A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability", 0-7803-8834-8/05/$20 ?2005 IEEE, 2005.
- Pak K. Chan, et al, Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming, IEEE Transactions on Computers, vol. 41, No. 8 (Aug. 1992): 920-93.
- S. Shanthala, C. P. Raj, "Design and VLSI Implementation of Pipelined Multiply Accumulate Unit", International Conference on ETET-09, pp 381-386, 2009.
- Sarabdeep Singh and dilip Kumar, "Design of Area and Power Efficient Modified Carry Select Adder", International Journal of Computer Application (November 2011), vol. 33 – No. 3.
- Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full-Adders for Energy-Ef?cient Arithmetic Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 19, No. 4, April 2011
- ] Deepa Sinha, Tripti Sharma, k. G. Sharma, Prof. B. P. Singh, "Design and Analysis of low Power 1-bit Full Adder Cell",IEEE, 2011.
- H. S. Dhillon , and A. Mitra , "A Reduced- Multiplication Algorithm for Digital Arithmetic ," International Journal of Computational and Mathematical Sciences, pp. 64-69, Spring 2008.
- Shubin. V. V, "Analysis and Comparison of Ripple Carry Full Adders by Speed", Micro/Nano Technologies and Electron Devices (EDM),2010, International Conference and Seminar on, pp. 132- 135,2010.
Index Terms
Keywords