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Reseach Article

Performance Analysis of Low Complexity Error Correcting Codes

by Banaful Paul, Asif Md. Siddique, Rabiul Islam, Md. Jahidul Alam
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 59 - Number 14
Year of Publication: 2012
Authors: Banaful Paul, Asif Md. Siddique, Rabiul Islam, Md. Jahidul Alam
10.5120/9613-4246

Banaful Paul, Asif Md. Siddique, Rabiul Islam, Md. Jahidul Alam . Performance Analysis of Low Complexity Error Correcting Codes. International Journal of Computer Applications. 59, 14 ( December 2012), 1-4. DOI=10.5120/9613-4246

@article{ 10.5120/9613-4246,
author = { Banaful Paul, Asif Md. Siddique, Rabiul Islam, Md. Jahidul Alam },
title = { Performance Analysis of Low Complexity Error Correcting Codes },
journal = { International Journal of Computer Applications },
issue_date = { December 2012 },
volume = { 59 },
number = { 14 },
month = { December },
year = { 2012 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume59/number14/9613-4246/ },
doi = { 10.5120/9613-4246 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:04:53.273362+05:30
%A Banaful Paul
%A Asif Md. Siddique
%A Rabiul Islam
%A Md. Jahidul Alam
%T Performance Analysis of Low Complexity Error Correcting Codes
%J International Journal of Computer Applications
%@ 0975-8887
%V 59
%N 14
%P 1-4
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

From Shannon limit it is known that, for a particular bandwidth and noise characteristics, there exists a maximum rate at which data can be transmitted with arbitrarily small number of errors. Coding schemes are utilized to improve the data transmission efficiency. The paper aims to represent the comparative performance analysis of Low Density Parity Check (LDPC) codes and Bose-Chaudhuri-Hocquenghem (BCH) codes in transmitting data over noisy channel for different parameters. The performance of LDPC block codes is simulated for different decoding schemes and code rates. Performance analysis of LDPC codes is also shown for regular and irregular codes. For fixed error correcting capability, the BCH coding scheme is further simulated for different code length with increasing code length. The simulated output is worthwhile to analyze the performance of a communication system before the physical implementation of the system.

References
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Index Terms

Computer Science
Information Sciences

Keywords

LDPC BCH Code rateifx