The week's pick
Random Articles
Reseach Article
FPGA based High Speed Double Precision Floating Point Divider
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 60 - Number 13 |
| Year of Publication: 2012 |
| Authors: Addanki Purna Ramesh, Dhanalakshmi Balusu |
10.5120/9752-4332
|
Addanki Purna Ramesh, Dhanalakshmi Balusu . FPGA based High Speed Double Precision Floating Point Divider. International Journal of Computer Applications. 60, 13 ( December 2012), 21-26. DOI=10.5120/9752-4332
Abstract
Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. Division is the third basic operation of arithmetic. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper we describe an implementation of high speed IEEE 754 double precision floating point divider using digit recurrence algorithm and targeted for Xilinx Virtex-6 Field Programmable Gate Array. Verilog is used to implement the design. The implemented design achieves 344. 89 MFlops and this design occupies 653 slices. It handles the overflow, underflow and rounding mode.
References
- Shamna. K, and S. R Ramesh," Design and Implementation of an Optimized Double Precision Floating Point Divider on FPGA" International Journal of Advanced Science and Technology Vol. 18, pp. 41-48, May, 2010.
- K. Scott Hemmert and Keith D. Underwood "Floating Point Divider Design for FPGAs", IEEE Transaction on very large scale integration systems,vol. 15, No. 1, pp. 115-118,Jan 2007.
- Anuja Jayraj Thakkar and Abdel Ejnioui "Design and Implementation of Double Precision Floating Point Divider and Square Root Operations on FPGAs,"IEEE Conference on field programmable technology, 2006.
- X . Wang and B. E Nelson, "Tradeoffs of designing floating point division and square root on virtex fpgas", International Conference on engineering of reconfigurable systems and algorithms, 2004.
- S. Paschalakis and P. Lee,"Double precision Floating point arithmetic on fpgas "IEEE Conference on field programmable technology, 2003.
- S. F. Oberman and M. J. Flynn, "Division Algorithms and Implementations," IEEE Trans. Computers, vol. 46, no. 8, pp. 833-854, Aug. 1997
- Peter Soderquist, Miriam Leeser, "Division and Square Root: Choosing the Right Implementation,"IEEE Micro, vol. 17, no. 4, pp. 56-66, July/Aug. 1997
- S. F. Oberman and M. J. Flynn, "Design Issues in Division and Other Floating-Point Operations," IEEE Trans. Computers, vol. 46, no. 2, pp. 154-161, Feb. 1997
Index Terms
Keywords