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An Efficient Design of 3bit and 4bit Flash ADC
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 61 - Number 11 |
| Year of Publication: 2013 |
| Authors: Arunkumar P Chavan, Rekha G, P Narashimaraja |
10.5120/9974-4802
|
Arunkumar P Chavan, Rekha G, P Narashimaraja . An Efficient Design of 3bit and 4bit Flash ADC. International Journal of Computer Applications. 61, 11 ( January 2013), 32-37. DOI=10.5120/9974-4802
Abstract
The performance of Flash Analog-to-Digital converter is greatly influenced by the choice of Comparator and Thermometer-to- Binary encoder design. The work describes the design and pre-simulation of a , 3bit and an 4bit analog to digital converter for low power CMOS. It requires 2N-1 comparators, an encoder to convert thermometer code to binary code. The design is simulated in cadence environment using spectre simulator under 90nm technology. The pre simulation results for the design shows a low power dissipation of 87uw for the comparator and 1. 05mW and 1. 984mW power dissipation for 3-bit and 4-bit Flash ADC respectively. The circuit operates with an input frequency of 25MHz and 1. 5V supply with a conversion time of 2. 162ns and 6. 182ns for 3-bit and 4-bit ADC respectively.
References
- Shubhara Yewale, Radheshyam Gamad "Design of Low Power and High SpeedMOS Comparator for A/D
- Converter application", Wireless Engineering and Technology, 2012, 3, 90-95.
- B. Razavi, "Deign of Analog CMOS Integrated Circuits," Tata McGraw-Hill, Delhi, 2002.
- R. Wang, K. Li, J. Zhang and B. Nie, "A High Speed High Resolution Latch Comparator For-Pipeline ADC," IEEE International Workshop on Anti-counterfeiting, Se- curity, Identification, Xiamen, 16-18 April 2007, pp. 28- 31.
- Y. Degerli, N. Fourches, M. Rouger and P. Lut, "Low Power Autozeroed High-Speed Comparator for the Read- out Chain of a CMOS Monolithic Active Pixel Sensor Based Vertex Detector," IEEE Transactions on Nuclear Science, Vol. 50, No. 5, 2003, pp. 1-21.
- Y. Sun, Y. S. Wang and F. C. Lai, "Low Power High Speed Switched Current Comparator," IEEE 14th Inter- national Conference, Ciechocinek, 21-23 June 2007, pp. 305-308.
- M. Panchore and R. S. Gamad, "Low Power and High Speed CMOS Comparator Design Using 0. 18 ?m Tech- nology," International Journal of Electronic Engineering Research, Research India Publications, Vol. 2, No. 1, 2010, pp. 71-77.
- W. Rong, W. Xiaobo and Y. Xiaolang, "A Dynamic CMOS Comparator with High Precision and Resolution," IEEE Proceedings of 7th International Conference on So- lid-State and Integrated Circuits Technology, 18-21 Oc- tober 2004, pp. 1567-1570.
- ShaileshRadhakrishnan, Mingzhen Wang, Chien-In Henry Chen,"Low-Power 4-b 2. 5GSPS Pipelined Flash Analog-to-Digital Converters in 3um CMOS", IEEE Instrumentation and Measurement Technology Conference, vol. 1, pp. 287 – 292, May. 2005.
- Chia-Nan Yeh and Yen-Tai Lai, "A Novel Flash Analog-to-Digital Converter", IEEE J, 2008.
- G. M. Yin, F. Op'tEynde, and W. Sansen, "A high-speed CMOS comparator with 8-bit resolution", IEEE J. Solid -State Circuits, vol. 27, 1992.
- A. V. Bapat, Dr. A. S. Gandhi, Dr. A. M. Dighe, "CMOS Implementation of Serial Flash Analog to Digital Converter", International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011
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