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A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

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International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 61 - Number 5
Year of Publication: 2013
Authors:
Tarun Kr. Gupta
Kavita Khare
10.5120/9923-4544

Tarun Kr. Gupta and Kavita Khare. Article: A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits. International Journal of Computer Applications 61(5):14-20, January 2013. Full text available. BibTeX

@article{key:article,
	author = {Tarun Kr. Gupta and Kavita Khare},
	title = {Article: A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {61},
	number = {5},
	pages = {14-20},
	month = {January},
	note = {Full text available}
}

Abstract

A new dual-threshold circuit technique is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type lea-kage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 34% to 57. 5% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 250C and 1100C temperatures the maximum leakage power saving of 99. 97% is achieved when compared to standard dual-threshold domino logic circuits in a 65nm CMOS technology.

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