CFP last date
22 April 2024
Reseach Article

A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits

by Tarun Kr. Gupta, Kavita Khare
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 61 - Number 5
Year of Publication: 2013
Authors: Tarun Kr. Gupta, Kavita Khare
10.5120/9923-4544

Tarun Kr. Gupta, Kavita Khare . A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits. International Journal of Computer Applications. 61, 5 ( January 2013), 14-20. DOI=10.5120/9923-4544

@article{ 10.5120/9923-4544,
author = { Tarun Kr. Gupta, Kavita Khare },
title = { A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 61 },
number = { 5 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 14-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume61/number5/9923-4544/ },
doi = { 10.5120/9923-4544 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:08:16.912943+05:30
%A Tarun Kr. Gupta
%A Kavita Khare
%T A New Dual-Threshold Technique for Leakage Reduction in 65nm Footerless Domino Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 61
%N 5
%P 14-20
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A new dual-threshold circuit technique is proposed in this paper for reducing the subthreshold and gate oxide leakage currents in idle and non idle mode of operation for footerless domino circuits. In this technique a p-type and an n-type lea-kage controlled transistors (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. For any combination of input, one of the LCT will operate near its cut off region and will increase the resistance between supply voltage and ground resulting in reduced leakage current. Furthermore, the leakage current is suppressed at the output inverter circuit by inserting a transistor below the n-type transistor of the inverter offering more resistive path between supply voltage and ground. The proposed technique is applied on benchmark circuits reduction of active power consumption is observed from 34% to 57. 5% at different temperature variations. For same benchmark circuits, operating at two clock modes and giving low and high inputs at 250C and 1100C temperatures the maximum leakage power saving of 99. 97% is achieved when compared to standard dual-threshold domino logic circuits in a 65nm CMOS technology.

References
  1. H. Mahmoodi-Meimand, K. Roy, "A Leakage-tolerant high fan-in dynamic circuit style", IEEE International Systems-On-Chip Conference, 2003, pp. 117-120.
  2. J. -S. Wang, S. -j. Shieh, C. Yeh, Y. -h. Yeh, "Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs", ISCAS, 2004, pp. 401-404
  3. V. Kursun and E. G. Friedman, "Domino logic with varia- ble threshold voltage keeper", IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 11, no. 6, 2003, pp. 1080-1093.
  4. Y. Taur and T. H. Hing, Fundamentals of Modern VLSI Devices, New York. USA: Cambridge University Press, 1998, ch. 3, pp. 120-128.
  5. Kaushik Roy, et al. , "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits", Proc. IEEE, vol. 91, no. 2, 2003, pp. 306-327.
  6. Y. Taur and T. H. Hing, Fundamentals of Modern VLSI Devices, New York. USA: Cambridge University Press, 1998, ch. 2, pp. 94-95.
  7. Y. Taur and T. H. Hing, Fundamentals of Modern VLSI Devices, New York. USA: Cambridge University Press, 1998, ch. 2, pp. 97-99.
  8. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Cir-cuit Design, New York. USA: Wiley Interscience Publi-cations, 2000, ch. 2, pp. 28-29.
  9. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Cir-cuit Design, New York. USA: Wiley Interscience Publi-cations, 2000, ch. 2, pp. 27-28.
  10. Z. Liu and V. Kursun, "Leakage power characteristics of dynamic circuits in nanometer CMOS technologies", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, 2006, pp. 692–696.
  11. H. Sasaki, M. Ono, T. Ohguro, S. Nakamura, M. Satio and Iwai, "1. 5nm direct-tuneling gate oxide Si MOS-FETs", IEEE Trans. Electron Devices, vol. 43, no. 8, 1996, pp. 1233-1242.
  12. Z. Liu and V. Kursun, "Leakage biased PMOS sleep switch dynamic circuits", IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, 2006, pp. 1093–1097.
  13. J. Kao, "Dual threshold voltage domino logic", in Proc. of the European Solid-State Circuits Conference, Sep-tember 1999, pp. 118-121.
  14. V. Kursun and E. G. Friedman, Multi-voltage CMOS Cir- cuit Design, Hoboken, NJ: Wiley, 2006
  15. Farshad Moradi and Ali Peiravi, "An Improved Noise-Tolerant Domino Logic Circuit for High Fan-in Gates", Proc. IEEE, 2005, pp. 116-121.
  16. M. C. Johnson, D. Somasekhar, L. Y. Chiou, and K. Roy, "Leakage control with efficient use of transistor stacks in single threshold CMOS", IEEE Trans. VLSI Syst. , vol. 10, 2002, pp. 1–5.
  17. S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. P. Chandrakasan, "Scaling of stack effect and its application for leakage reduction", IEEE ISLPLED, Aug. 2001, pp. 195–200.
  18. S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw, "Duet: An accurate leakage estimation and op-timization tool for dual-Vt circuits", IEEE Trans. VLSI Syst. , vol. 10, 2002, pp. 79–90.
Index Terms

Computer Science
Information Sciences

Keywords

Dual-Threshold Domino logic Subthreshold leakage Gate oxide tunneling Leakage current