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High-Speed Tree-based 64-Bit Binary Comparator using New Approach

by Anjuli, Satyajit Anand
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 61 - Number 5
Year of Publication: 2013
Authors: Anjuli, Satyajit Anand
10.5120/9928-4558

Anjuli, Satyajit Anand . High-Speed Tree-based 64-Bit Binary Comparator using New Approach. International Journal of Computer Applications. 61, 5 ( January 2013), 50-54. DOI=10.5120/9928-4558

@article{ 10.5120/9928-4558,
author = { Anjuli, Satyajit Anand },
title = { High-Speed Tree-based 64-Bit Binary Comparator using New Approach },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 61 },
number = { 5 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 50-54 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume61/number5/9928-4558/ },
doi = { 10.5120/9928-4558 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:08:19.074757+05:30
%A Anjuli
%A Satyajit Anand
%T High-Speed Tree-based 64-Bit Binary Comparator using New Approach
%J International Journal of Computer Applications
%@ 0975-8887
%V 61
%N 5
%P 50-54
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

High-speed tree-based 64-bit binary comparator: A New Approach is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means some modifications are done in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool.

References
  1. Pierce Chuang, David Li, and Manoj Sachdev, Fellow, IEEE "A Low-Power High-Performance Single-Cycle Tree -Based 64-Bit Binary Comparator" IEEE Transactions On Circuits and Systems—II: Express Briefs, Vol. 59, No. 2,February 2012.
  2. F. Frustaci, S. Perri, M. Lanuzza, and P. Corsonello, "A new low-power high-speed single-clock-cycle binary comparator," in Proc. IEEE. Int. Symp. Circuits Syst. , 2010, pp. 317–320.
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Index Terms

Computer Science
Information Sciences

Keywords

Binary comparator digital arithmetic

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