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Design Space Exploration for a Custom VLIW Architecture

by M.k.jain, Veena Ramnani
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 61 - Number 8
Year of Publication: 2013
Authors: M.k.jain, Veena Ramnani
10.5120/9951-4598

M.k.jain, Veena Ramnani . Design Space Exploration for a Custom VLIW Architecture. International Journal of Computer Applications. 61, 8 ( January 2013), 31-35. DOI=10.5120/9951-4598

@article{ 10.5120/9951-4598,
author = { M.k.jain, Veena Ramnani },
title = { Design Space Exploration for a Custom VLIW Architecture },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 61 },
number = { 8 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 31-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume61/number8/9951-4598/ },
doi = { 10.5120/9951-4598 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:08:36.288254+05:30
%A M.k.jain
%A Veena Ramnani
%T Design Space Exploration for a Custom VLIW Architecture
%J International Journal of Computer Applications
%@ 0975-8887
%V 61
%N 8
%P 31-35
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The increasing complexity of algorithms and embedded systems constraints has lead to advanced design methodologies. Hardware/Software co-design methodology has made it possible to find an optimal architecture for a given application by exploring the design space before building a real hardware prototype. The Design Space Exploration is basically exploring the various processor architectures in order to search for a processor architecture that satisfies different conflicting criteria such as chip area, speed, power consumption or on-chip memory requirements. The output is a set of different architectures representing the different tradeoffs. Retargetable compiler is an important tool in design space exploration (DSE). Retargetable compiler is capable of generating code for different target processors, by reusing most of the code. The objective of this research is to develop a retargetable compiler that can generate efficient code in terms of code size, cycle count and retargetability efforts for a VLIW processor.

References
  1. Jain,M. K. , Kumar,A. , Balakrishnan,M. and Gangwar,A. (2005) Customizing Embedded Processors for Specific Applications, In proceedings of Recent Trends in Practice and Theory of Information Technology, Proc. of NRB Seminar, 10-11 January 2005, NPOL, Cochin, pp. 261-284
  2. Jain, M. K. , Balakrishnan, M. and Kumar, A. (2001) ASIP Design Methodologies: Survey and Issues, In proceedings of the Fourteenth International Conference on VLSI Design, 2001, 3-7 Jan. 2001, Pages: 76-81
  3. Jain, M. K. , Balakrishnan, M. and Kumar A. (2004), Efficient Technique for Exploring Register File Size in ASIP Design', IEEE TCAD of VLSI, vol. 23, No. 12, pp. 1693-1699, Dec. 2004.
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  6. P. Faraboschi, G. Brown and al. , "LX: A technology platform for customizable VLIW embedded processing", Proc. of the 27th annual International Symposium of Computer Architecture, June 2000.
  7. Hewlett-Packard Laboratories, VEX Toolchain, http://www. hpl. hp. com/downloads/vex.
  8. Fisher Joseph A (1991), Global Code Generation for Instruction-Level Parallelism: Trace Scheduling-2. Workshop on Advanced Compilation Techniques for Novel Machine Architecture, Jerusalem, 1991
Index Terms

Computer Science
Information Sciences

Keywords

Retargetable Compilers VLIW ILP