CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Charge Redistribution based 8 bit SAR ADC

by Vijay V, Bhavya R, Vipula Singh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 62 - Number 1
Year of Publication: 2013
Authors: Vijay V, Bhavya R, Vipula Singh
10.5120/10042-4625

Vijay V, Bhavya R, Vipula Singh . Charge Redistribution based 8 bit SAR ADC. International Journal of Computer Applications. 62, 1 ( January 2013), 6-9. DOI=10.5120/10042-4625

@article{ 10.5120/10042-4625,
author = { Vijay V, Bhavya R, Vipula Singh },
title = { Charge Redistribution based 8 bit SAR ADC },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 62 },
number = { 1 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 6-9 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume62/number1/10042-4625/ },
doi = { 10.5120/10042-4625 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:11:06.998409+05:30
%A Vijay V
%A Bhavya R
%A Vipula Singh
%T Charge Redistribution based 8 bit SAR ADC
%J International Journal of Computer Applications
%@ 0975-8887
%V 62
%N 1
%P 6-9
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

An 8-bit 10 MS/s SAR A/D converter is presented. In the circuit design, a capacitor switched D/A Converter architecture, Dynamic latched comparator architecture and low power SAR logic are utilized. Design challenges and considerations are also discussed. This proposed converter is implemented based on 0. 29um CMOS logic process. With a 3. 3 V analog supply and a 5 V digital supply, the differential and integral nonlinearity are measured to be less than 0. 36 LSB and 0. 69 LSB respectively. With an input frequency of 625 KHz at 10 MS/s sampling rate and the power dissipation is measured to be 6. 62 mW.

References
  1. J. L. McCreary and P. R. Gray," All-MOS Charge Redistribution Analog- to – Digital Conversion Techniques- Part 1," IEEE Journal of Solid State Circuits,vol. SC -10, no. 6 , pp. 371-379,1975.
  3. B. Razavi and B. A. Wooley, "A 12-b 5-MSample/s Two-Step CMOS A/D Converter," IEEE JSSC Vol. 27, No. 12, December 1992.
  4. F. Maloberti, Design of analog-digital VLSI circuits for telecommunications and signal processing, Layout of Analog and Mixed Analog-digital Circuits, Prentice Hall, second edition, 1994, J. E. Franca and Y. Tsividis edited.
  5. M. J. M. Pelgrom, A. C. J. Duenmaijer and A. P. G. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid-State Circuits, vol. 24, no. 5, Oct. , 1989.
  6. P. M. Figueiredo and J. C. Vital, "Kickback Noise Reduction Techniques for CMOS Latched Comparators," IEEE Transactions on Circuits and Systems, vol. 53, no. 7, July, 2007.
  7. M. D. Scott, B. E. Boser and K. S. J. Pister, "An Ultralow-Energy ADC for Smart Dust," IEEE Journal of Solid-State Circuits, vol. 38, no. 7, July, 2003.
Index Terms

Computer Science
Information Sciences

Keywords

Analog to Digital Converters (ADC) Digital to Analog Converter (DAC) Successive Approximation Registers (SAR) Comparator Latch

Powered by PhDFocusTM