CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool

by Chakshu Goel, Puneet Jain, Gurjeevan Singh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 62 - Number 16
Year of Publication: 2013
Authors: Chakshu Goel, Puneet Jain, Gurjeevan Singh
10.5120/10166-4958

Chakshu Goel, Puneet Jain, Gurjeevan Singh . Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool. International Journal of Computer Applications. 62, 16 ( January 2013), 30-33. DOI=10.5120/10166-4958

@article{ 10.5120/10166-4958,
author = { Chakshu Goel, Puneet Jain, Gurjeevan Singh },
title = { Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 62 },
number = { 16 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 30-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume62/number16/10166-4958/ },
doi = { 10.5120/10166-4958 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:12:00.467120+05:30
%A Chakshu Goel
%A Puneet Jain
%A Gurjeevan Singh
%T Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool
%J International Journal of Computer Applications
%@ 0975-8887
%V 62
%N 16
%P 30-33
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this Research Paper, the focus is on the analysis and simulation of the Adder cell which is slightly different as compared to the existing circuits and optimized for Average Power Dissipation. In this paper the adder cell is modified circuit in such a way that it controls the overall capacitances during the Sum and Carry evaluation and will optimize the total capacitance that results in the decrease of the Average Power dissipation. The circuit is characterized by using HSPICE in a 180 nanometer (nm) with supply voltage of 1. 8 volt and threshold voltage is 0. 40 volts.

References
  1. Jan . M. Rabaey Anantha Chandrakasan & Borivoje Nikolic , ( 2003) Digital Integrated Circuits, Prentice Hall Electronics and VLSI Series, Second Edition
  2. Damu Radhakrishnan , "A NEW LOW POWER CMOS FULL ADDER" MICC and ISCE '99 Proc. , Nov. 1999, Melaka, Malaysia.
  3. Keivan Navi and Omid Kavehei, "Low Power and High-Performance 1-BitCMOS Full-Adder Cell", Journal of computers, vol. 3, no. 2, February 2008.
  4. Ilham Hassoune, Denis Flandre, "ULPFA: A New Efficient Design of a Power-Aware Full Adder" IEEE Transactions on circuits and systems -1 regular papers, vol. 7, No. 8, august 2010.
  5. Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS full adder for energy efficient arithmetic applications" IEEE Transactions on VERY LARGE SCALE INTEGRATION (VLSI) Systems, vol. 19, no. 4, april 2011.
  6. Website,http://www. tannereda. com/support/latest-version
  7. Website,http://www. mosis. com/products/fab/vendors/tsmc/ts mc-kits. html
  8. Website;http://www. microwind. net
  9. R. Jacob Baker, "CMOS circuit design, layout, simulation", Wiley –IEEE Press, ISBN 978- 0-470-88132 -3, 3rd Edition 2010.
Index Terms

Computer Science
Information Sciences

Keywords

Full Adder Tanner Tool CMOS circuit VLSI

Powered by PhDFocusTM