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Hardware Implementation of DSP Filter on FPGAs
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 62 - Number 16 |
| Year of Publication: 2013 |
| Authors: Apurva Singh Chauhan, A. Mukund Lal, Varun Maheshwari, D. Bhagwan Das |
10.5120/10167-4969
|
Apurva Singh Chauhan, A. Mukund Lal, Varun Maheshwari, D. Bhagwan Das . Hardware Implementation of DSP Filter on FPGAs. International Journal of Computer Applications. 62, 16 ( January 2013), 34-37. DOI=10.5120/10167-4969
Abstract
This paper describes the hardware implemention of Digital signal processing filters on FPGAs (Field programmable gate array). Traditionally, digital signal processing (DSP) algorithms are implemented using general purpose programmable DSP chips for low-rate applications. Alternatively, special purpose fixed function DSP chipsets and application specific integrated circuits (ASICs) are used for high-performance application. Technological amelioration by Xilinx on FPGAs in the past few years has opened new paths for engineers to design various applications on FPGAs. The FPGAs assert the high explicitness of the ASIC while avoiding its high development cost and its inability to accommodate design modifications after production. Highly adaptable and design-flexibility, FPGAs provide optimal device utilization through conservation of board space and system power important advantages not available with many stand-alone DSP chips.
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