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FPGA Implementation of 2D and 3D Image Enhancement Chip in HDL Environment

by Priyanka Saini, Adesh Kumar, Neha Singh
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 62 - Number 21
Year of Publication: 2013
Authors: Priyanka Saini, Adesh Kumar, Neha Singh
10.5120/10221-4981

Priyanka Saini, Adesh Kumar, Neha Singh . FPGA Implementation of 2D and 3D Image Enhancement Chip in HDL Environment. International Journal of Computer Applications. 62, 21 ( January 2013), 24-31. DOI=10.5120/10221-4981

@article{ 10.5120/10221-4981,
author = { Priyanka Saini, Adesh Kumar, Neha Singh },
title = { FPGA Implementation of 2D and 3D Image Enhancement Chip in HDL Environment },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 62 },
number = { 21 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 24-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume62/number21/10221-4981/ },
doi = { 10.5120/10221-4981 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:12:30.608593+05:30
%A Priyanka Saini
%A Adesh Kumar
%A Neha Singh
%T FPGA Implementation of 2D and 3D Image Enhancement Chip in HDL Environment
%J International Journal of Computer Applications
%@ 0975-8887
%V 62
%N 21
%P 24-31
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Digital image processing is an ever expanding and dynamic area with applications reaching out into everyday life such as medicine, space exploration, surveillance, authentication, automated industry inspection and many more areas. Applications such as these involve different processes like image enhancement and object detection. Implementing such applications on a general purpose computer can be easier, but not very time efficient due to additional constraints on memory and other peripheral devices. Hardware implementation for application specific can offer much greater speed than a software implementation. With the advancement in the Very Large Scale of Integration (VLSI) technology hardware implementation has become an attractive alternative. Implementing complex computation tasks on hardware and by exploiting parallelism and pipelining in algorithms yield significant reduction in execution times. It has been observed that most of the work has been done either in C and JAVA. No work has been done in the VHDL to design and develop the chip for image enhancement algorithms. Intensity transformation is used to enhance the size of image pixels. The chip design for 2D and 3D image enhancement is done in Xilinx 14. 2 software. Image enhanced values are verified with the help of waveform editor of Modelism software, Modelsim SE 10. 1b.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Very High Speed Integrated Circuit hardware Description language (VHDL) Very Large Scale of Integration (VLSI) Field Programmable Gate Array (FPGA)

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