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Reseach Article

FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration

by Mahmoud A. M. Alshewimy, Ahmet Sertbas
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 65 - Number 11
Year of Publication: 2013
Authors: Mahmoud A. M. Alshewimy, Ahmet Sertbas
10.5120/10968-6100

Mahmoud A. M. Alshewimy, Ahmet Sertbas . FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration. International Journal of Computer Applications. 65, 11 ( March 2013), 15-19. DOI=10.5120/10968-6100

@article{ 10.5120/10968-6100,
author = { Mahmoud A. M. Alshewimy, Ahmet Sertbas },
title = { FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 65 },
number = { 11 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 15-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume65/number11/10968-6100/ },
doi = { 10.5120/10968-6100 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:18:35.390853+05:30
%A Mahmoud A. M. Alshewimy
%A Ahmet Sertbas
%T FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration
%J International Journal of Computer Applications
%@ 0975-8887
%V 65
%N 11
%P 15-19
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents FPGA-based design of hybrid adder with the optimal bit-width configuration(out of alarge number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraicoptimization model for the hybrid adderis built to produce the best choice of types and bit-widths of the sub-adders. In context of this work, several classes of parallel adders are designed and its performance is evaluated to serve as sub-adders inside the hybrid adder. The results show that the proposed model gains a high flexibility in allowing design tradeoffs between the performance criteria delay and areaand successfully to generate the optimalbit-width configurations of the hybrid adder.

References
  1. Lynch, T. and Swartzlander, E. E. ,"A spanning Tree Carry Lookahead Adder", IEEE Trans. on Computers, 41 (August 1992), 931-939,1993.
  2. Wang, Y. , Pai, C. , and Song, X. , "The Design of Hybrid Carry-Lookahead/Carry–Select Adders", IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 1, 2002.
  3. Li, J. , Yu, J. and Huang, Y. , "A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability", in Proc. 15th VLSI/CAD Symp. , (Pintung), 2005.
  4. Lakshmanan, Meaamar,A. , and Othman,M. ,"High-Speed Hybrid Parallel-Prefix Carry-SelectAdder Using Ling's Algorithm", ICSE2006 Proc. , Kuala Lumpur, Malaysia, 2006.
  5. Zimmermann, R. 1997. Binary Adder Architectures for Cell – Based VLSI and their Synthesis, Thesis (Phd), Swiss Federal Institute of Technology, Zurich.
  6. PARHAMI, B. 2000. Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, USA.
  7. Sklansky,J. , "Conditional sum addition logic", IRE Trans. Electron. Comput. , vol. EC-9, no. 6, pp. 226–231, June 1960.
  8. Brent,R. P. and Kung,H. T. , "A regular layout for parallel adders", IEEE Trans. Comput. , vol. 31, no. 3, pp. 260–264, Mar. 1982.
  9. Vanderbei, R. J. 2001. Linear Programming: Foundations and Extensions. 2nd Ed. , USA.
Index Terms

Computer Science
Information Sciences

Keywords

Hybrid adder FPGA optimal algebraic delay area