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Designing and Simulating a 2.4 GHz Integer-N Frequency Synthesizer with 1 MHz Frequency Step
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 66 - Number 3 |
| Year of Publication: 2013 |
| Authors: Samir Kameche, Mohammed Feham |
10.5120/11062-5976
|
Samir Kameche, Mohammed Feham . Designing and Simulating a 2.4 GHz Integer-N Frequency Synthesizer with 1 MHz Frequency Step. International Journal of Computer Applications. 66, 3 ( March 2013), 9-12. DOI=10.5120/11062-5976
Abstract
This article consists on the design and the simulation of a 2. 4 GHz Integer-N Frequency Synthesizer with 1 MHz Frequency Step which can be used for exchanging data over short distances (using short-wavelength radio transmissions in the ISM band from 2400–2480 MHz) from fixed and mobile devices, creating personal area networks (PANs) with high levels of security. The effects of the sideband's spurious noise on the adjacent channels and the phase noise in each component in the circuit on system performances are discussed. An accurate transient analysis of the PLL system is also presented in this work. The obtained output spectrum presents a noise density of -82dBc/Hz at an offset frequency of 1MHz, a switching time for a frequency jump of 80 MHz about 50. 83 µS. The essential component used to design the PLL frequency synthesizer is ADF4106 from Analog Devices, Inc.
References
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