Call for Paper - March 2023 Edition
IJCA solicits original research papers for the March 2023 Edition. Last date of manuscript submission is February 20, 2023. Read More

Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder

Print
PDF
International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 67 - Number 6
Year of Publication: 2013
Authors:
Vishnupriya. A
Sudarmani. R
10.5120/11401-6717

Vishnupriya. A and Sudarmani. R. Article: Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder. International Journal of Computer Applications 67(6):33-38, April 2013. Full text available. BibTeX

@article{key:article,
	author = {Vishnupriya. A and Sudarmani. R},
	title = {Article: Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {67},
	number = {6},
	pages = {33-38},
	month = {April},
	note = {Full text available}
}

Abstract

High speed and low power multiplier circuits are highly demanded in VLSI design. In this paper, a new approach for high speed and low power multiplier design with less number of gate counts is proposed. In the Ripple Counter–based multiplier design, the number of computational clock cycles is reduced to n for n * n multiplication where n is the word length or the number of bits, which was 2n in the conventional CSAS multiplier. The Ripple Carry Adder (RCA) in the Counter-based design is replaced with Kogge-Stone adder (KSA) for reducing the average connection delay. For reducing the total equivalent gate count and power, the full adder with alternate logic is implemented along with KSA in the multiplier architecture. In our paper, 27. 21% and 31. 53% of the total power has been reduced for unsigned and signed number multiplication respectively.

References

  • A. K. Lenstra and E. Verheul, "Selecting cryptographic key sizes," J. Cryptology, vol. 14, no. 4, pp. 255–293, 2001.
  • N. R. Strader and V. T. Rhyne, "A canonical bit-sequential multiplier," IEEE Trans. Comput. , vol. C-31, no. 8, pp. 791–795, August 1982.
  • R. Gnanasekaran, "On a bit-serial input and bit-serial output multiplier" IEEE Trans. Comput. , vol. C-32, no. 9, pp. 878–880, 1983.
  • P. Ienne and M. A Viredaz, "Bit-serial multipliers and squarers," IEEE Trans. Comput. , vol. 43, no. 12, pp. 1445–1450, December 1994.
  • Mark Vesterbacka, Kent Palmkvist, and Lars Wanhammar, "Serial squarers and serial/serial multipliers".
  • A. D. Booth, "A signed binary multiplication technique," Quarterly J. Mechan. Appl. Math. , vol. 4, no. 2, pp. 236–240, August 1951.
  • C. P. Lerogue, P. Gerard, and J. S. Colardelle, " A fast 16- bit NMOS parallel multiplier", IEEE Journal of Solid-state circuits, Vol. 19, no. 3, pp. 338-342, Mar 1984.
  • Jin-HaoTu and Lan-Da Van, "Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers" IEEE Transactions on computers, vol. 58, No. 10, October 2009.
  • A. Dandapat, S. Ghosal, P. Sarkar, D. Mukhopadhyay (2009), "A 1. 2- ns16×16-Bit Binary Multiplier Using High Speed Compressors", International Journal of Electrical, Computer, and Systems Engineering, pp. 234-239, 2009.
  • William J. Stenzel, William J. Kumitz , Gilles H. Garcia, " Compact High- Speed Parallel Multiplication Scheme," IEEE Trans. Comput. , C-26:948-957, 1977.
  • S. Haynal and B. Parhami, "Arithmetic structures for inner-product and other computations based on a latency-free bit-serial multiplier design," presented at the 13th Asilomar Conf. Signals, Syst. Comput. , Geneva, Switzerland, 1996.
  • ManasRanjanMeher, Ching-ChuenJong,Chip-Hong Chang, "High-Speed and Low-Power Serial Accumulator for Serial/Parallel Multiplier" IEEE Xplore, 2010.
  • B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2009.
  • R. Menon and D. Radhakrishnan, "High performance 5:2 compressor architectures," IEE Proc-Circuits Devices Syst. , vol. 153, no. 5, pp. 447–452, Oct. 2006.
  • R. Gnanasekaran, "A fast serial-parallel binary multiplier,"IEEE Trans. Comput. , vol. C-34, no. 8, pp. 741–744, August 1985.
  • ManasRanjanMeher,ChingChuen Jong, Chip-Hong Chang, "A High Bit Rate Serial-Serial Multiplier with On-the-Fly Accumulation by Asynchronous Counters,"IEEE transactions on Very Large Scale Integration (VLSI) systems, 2011.
  • Y. Kim and L. S . Kim, "64-bit carry-select adder with reduced area," Electron. Lett. , vol. 37, no. 10, May 2001.
  • R. P. Brent and H. T. Kung, "ARegular Layout for Parallel Adders," IEEE Transactions on Computers, vol. C-31, no. 3, pp. 260–264, 1982.
  • J. Sklansky, "Conditional-sum addition logic," IRE Transactions on Electronic Computers, vol. 9, pp. 226–231, 1960.
  • http://en. wikipedia. org/wiki/Kogge%E2%80%93Stone_adder
  • Haridimos T. Vergos and GiorgosDimitrakopoulos, "On Modulo 2n+1 Adder Design", IEEE transactions on computers, vol. 61, no. 2, February 2012.
  • J. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hill, Second Edition, 2003.
  • S. Ghosh et al. , "Tolerance to small delay defects by adaptive clock stretches," IOLTS, 2007.
  • P. Ndai et al. , "Fine-grained redundancy in adders," ISQED, 2007.
  • W. J. Townsend et al. , "Quadruple time redundancy adders," DFT, 2003.
  • B. W. Johnson, "Design and analysis of fault tolerant digital systems," Addison Wesley Publishing Company, 1989.
  • J. H. Patel et al. , "Concurrent error detection in ALUs by recomputing with shifted operands," Trans. Comput. , 1982.
  • K. Wu et al. , "Algorithm level Re-computing with shifted operands - a register transfer level concurrent error detection technique," ITC, 2000.
  • Aguirre, M. , M. Linares, "An Alternative Logic Approach to Implement High-Speed Low-Power Full Adder Cells", In:Proceedings of 18th annual symposium on Integrated circuits and system design, pp. 166-171, 2005.
  • Junming, L et al, "A Novel 10-Transistor Low-Power High-Speed Full Adder Cell", In: Proceedings of IEEE 6th International Conf. Solid-State & Integrated-Circuit Technology, Shanghai Jiao Tong Univ. , China, 2001.
  • Shalem, R. , E. John, L. K. John, "A novel low power energy recovery full adder cell", In: Proceedings of The Ninth Great Lakes Symposium on VLSI, Ann Arbor, MI, USA, 1999.
  • Fayed, A. A. , M. A. Bayoumi, "A Low Power 10-Transistor Full Adder Cell for Embedded Architectures", In: IEEE International Symposium on Circuits & Systems Design, Sydney, Australia, pp. 226-229, 2001.
  • Radhakrishnan, D. , A. P. Preethy, "Low-power CMOS pass logic 4-2 compressor for high-speed multiplication", In: Proceedings of the 43rd IEEE Midwest Symposium Circuits & Systems, pp. 1296-1298, 2000.
  • N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J. Solid-State Circuits, vol. 27, no. 5, May 1992.
  • Mariano Aguirre-Hernandez and Monico Linares-Aranda, "CMOS Full-Adders for Energy-Efficient Arithmetic Applications" IEEE transactions on very large scale integration (VLSI) systems, Vol. 19, no. 4, April 2011.