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Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 67 - Number 6
Year of Publication: 2013
Vishnupriya. A
Sudarmani. R

Vishnupriya. A and Sudarmani. R. Article: Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder. International Journal of Computer Applications 67(6):33-38, April 2013. Full text available. BibTeX

	author = {Vishnupriya. A and Sudarmani. R},
	title = {Article: Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {67},
	number = {6},
	pages = {33-38},
	month = {April},
	note = {Full text available}


High speed and low power multiplier circuits are highly demanded in VLSI design. In this paper, a new approach for high speed and low power multiplier design with less number of gate counts is proposed. In the Ripple Counter–based multiplier design, the number of computational clock cycles is reduced to n for n * n multiplication where n is the word length or the number of bits, which was 2n in the conventional CSAS multiplier. The Ripple Carry Adder (RCA) in the Counter-based design is replaced with Kogge-Stone adder (KSA) for reducing the average connection delay. For reducing the total equivalent gate count and power, the full adder with alternate logic is implemented along with KSA in the multiplier architecture. In our paper, 27. 21% and 31. 53% of the total power has been reduced for unsigned and signed number multiplication respectively.


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