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Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA

by Navdeep Kaur, Rajeev Kumar Patial
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 68 - Number 16
Year of Publication: 2013
Authors: Navdeep Kaur, Rajeev Kumar Patial
10.5120/11666-7261

Navdeep Kaur, Rajeev Kumar Patial . Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA. International Journal of Computer Applications. 68, 16 ( April 2013), 38-41. DOI=10.5120/11666-7261

@article{ 10.5120/11666-7261,
author = { Navdeep Kaur, Rajeev Kumar Patial },
title = { Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA },
journal = { International Journal of Computer Applications },
issue_date = { April 2013 },
volume = { 68 },
number = { 16 },
month = { April },
year = { 2013 },
issn = { 0975-8887 },
pages = { 38-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume68/number16/11666-7261/ },
doi = { 10.5120/11666-7261 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:28:03.838078+05:30
%A Navdeep Kaur
%A Rajeev Kumar Patial
%T Implementation of Modified Booth Multiplier using Pipeline Technique on FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 68
%N 16
%P 38-41
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents 16×16 bit Radix-4 Modified Booth's Multiplier (MBM) optimized for high speed multiplication by using pipeline Technique. This paper aims at reduction of hardware utilization. This is accomplished by the use of 3:2 compressor adders. An efficient VHDL code has been written, successfully simulated on Modelsim 10. 2 simulator and Xilinx 12. 4 navigator is used for synthesizing the code. Simulation result shows the clock period of 2. 689ns. The selected device to synthesize the code is xc3s500e-4pq208 of Sartan-3E family. The area utilization is shown as 222 numbers of slices and 383 numbers of LUTs.

References
  1. Wen-Chang Yeh and Chein-Wei Jen, "High-speed Booth encoded parallel multiplier design", IEEE Transaction on Computers, vol. 49, pp. 692-701, July 2000.
  2. A. R. Cooper , " Parallel architecture modified Booth multiplier" IEEE Proceedings, Vol. 135, Pt. G, No. 3, June 1988.
  3. A. D. Booth, "A signed binary multiplication technique", Quarterly J. Mechanical and Applied Math, vol. 4, pp. 236-240, 1951.
  4. O. L. Mac-Sorley, "High Speed Arithmetic in Binary Computers", Proceedings of IRE, Vol. 49, No. 1, January, 1961.
  5. D. Jackuline Moni, P. Eben Sophia, "Design of low power and high speed Configurable Booth Multiplier" IEEE Transaction, 2011, 978-1-4244-8679.
  6. Hwang-Cherng Chow and I-Chyn Wey, "A 3. 3V 1GHz high speed pipelined Booth multiplier", Proceedings of IEEE ISCAS, vol. 1, pp. 457-460. ,May 2002 .
  7. Soojin Kim and Kyeongsoon Cho. , "Design of High speed Modified Booth Multipliers Operating at GHz Ranges", World Academy of Science, Engineering and Technology, 2010.
  8. Chetan Gupta, "Design and implementation of a 32 bit MAC unit with pipelined variable stage Carry Select Adder" Electronics Dept. , Thapar University, June 2012.
  9. 'Modified Booth Multiplier' Digital Electronics Project 2 in 2008.
  10. J. Fadavi-Ardekani, "M × N booth encoded multiplier generator using optimized Wallace trees", IEEE Transaction on Very Large Scale Integration (VLSI) System, vol. 1, pp. 120–125, 1993.
  11. S. F. Hsiao, M. R. Jiang, and J. S. Yeh, "Design of high speed low-power 3-2 counter and 4-2 compressor for fast multipliers," Electron. Lett, vol. 34, no. 4, pp. 341–343, 1998
  12. Kulvir Singh Research Scholar, Dilip Kumar, "Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique" International Journal of Computer Applications (0975 – 8887) Volume 44– No14, April 2012.
  13. P. J. ; De Michelli, G. , "Circuit and Architecture Trade for High-Speed Multiplication", IEEE Journal Solid State Circuits, vol. 26, pp. 1184-1198, Sept. 1991.
  14. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electron Computers, vol. EC-13, pp. 14–17, 1964.
  15. V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers in Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A Chandrakasan, IEEE Press, 2000.
  16. S. B. Tatapudi and J. G. Delgado-Frias, "Designing pipelined systems with a clock period Approaching pipeline register delay," Proceedings of IEEE MWSCAS, vol. 1, pp. 871-874, Aug. 2005.
Index Terms

Computer Science
Information Sciences

Keywords

Compressor Modified Booth Recoding Pipelining Radix-4 Xilinx navigator

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