The week's pick
Random Articles
Reseach Article
Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 68 - Number 9 |
| Year of Publication: 2013 |
| Authors: Karna Sharma, Manan Sethi, Paanshul Dobriyal, Geetanjali Sharma |
10.5120/11608-6984
|
Karna Sharma, Manan Sethi, Paanshul Dobriyal, Geetanjali Sharma . Designing a Novel Power Efficient D- Flip-Flop using Forced Stack Technique. International Journal of Computer Applications. 68, 9 ( April 2013), 25-30. DOI=10.5120/11608-6984
Abstract
In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30% to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper various power efficient flip- flops with low power clock distribution network are examined. Among these flips-flops low Power Clocked Pass Transistor Flip-Flop (LCPTFF) consumes least power than Clocked Pair Shared Flip-Flop (CPSFF), Conditional Data Mapping Flip-Flop and Conditional Discharge Flip-Flop (CDFF). We propose a novel Low Power Forced Stack Clocked Pass Transistor Flip-Flop (LP-FSCPTFF) which reduces the power consumption by approximately 30. 1% to 83. 93% at 500MHz and 25. 5% to 90. 1% at 750MHz as compared to original LCPTFF. The simulation is carried out on Tanner EDA v13. 0 at 90nm on different voltages at 500MHz and 750MHz. The temperature variation of different flip-flops is also shown at 5 °C, 2 5 °C and 50 °C.
References
- M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp. 3-56, Jan. 1996.
- S. M. Kang, Y. Leblebici "CMOS Digital Integrated Circuits analysis and design" third edition, TMH, 2003.
- A. Keshavarzi, K. Roy, and C. F. Hawkins, "Intrinsic leakage in low power deep submicron CMOS ICs," in Proc. Int. Test Conf. , pp. 146– 155, 1997.
- Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng "Design of Sequential Elements for Low Power Clocking System" IEEE Transaction of Very large Scale Integration July 2010.
- N. Weste and D. Harris, "CMOS VLSI Design". Reading, MA: Addison Wesley, 2004.
- H. Upadhyay, A. Choubey, K. Nigam "Comparison Among Different CMOS Inverterwith Stack Keeper approach in VLSI design" International Journal of Engineering Research and Applications (IJERA), Vol. 2, Issue 3, May-Jun 2012, pp. 640-646.
- S H Kim, Vincent J Mooney "Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design", Very Large Scale integration,2006 IFIP International Conference
- P. Dobriyal, K. Sharma, M. Sethi, G. Sharma "A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS Technique",2013 3rd IEEE International Advance Computing Conference (IACC).
- P. Zhao, T. K. Darwish, and M. A. Bayoumi, "High-Performance and Low-Power Conditional Discharge Flip-Flop", IEEE transactions on very large scale integration (VLSI) systems, vol. 12 no. 5, May 2004.
- T. Kavitha, Dr. V. Sumalatha "A New Reduced Clock Power Flip-flop for Future SOC Applications". International Journal of Computer Trends and Technology, volume3Issue4, 2012.
- C. K. Teh, M. Hamada, T. Fujita,H. Hara, N. Ikumi, and Y. Oowaki, "Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems". IEEE Transactions on very large scale integration (VLSI) systems, vol. 14, no. 12,December 2006
- F. Mohammad, L. A. Abhilasand P. Srinivas"A new parallel counter architecture with reduced transistor count for power and area optimization", international conference on Electrical and Electronics Engineering, Sept. , 2012.
- BhuvanaS, SangeethaR"A Survey on Sequential Elements for Low Power Clocking System", Journal of Computer Applications ISSN: 0974 – 1925, Volume-5, Issue EICA2012-3, and February 10, 2012.
- P. Saini, R. Mehra "Leakage Power Reduction in CMOS VLSI Circuits", International Journal of Computer Applications (0975 – 8887)Volume 55– No. 8, October 2012.
Index Terms
Keywords