The week's pick
Reseach Article
Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 69 - Number 10 |
| Year of Publication: 2013 |
| Authors: Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma |
10.5120/11881-7696
|
Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma . Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic. International Journal of Computer Applications. 69, 10 ( May 2013), 32-35. DOI=10.5120/11881-7696
Abstract
In today's techno-savvy world the need of the hour is to develop devices which are power efficient as well as occupy very less area. VLSI circuits have proved to be the vital choice for most of the design engineers in order to reduce power consumption in any device. The most basic operation in any processor circuitry involves addition. Carry Select Adder (CSA) is a high speed adder and its structure reveals that there exists a possibility of reducing area and power dissipation of the circuit. This paper presents power and delay analysis of 16-Bit Square Root CSA implemented through Hybrid PTL/CMOS logic . It examines the performance of the proposed design in terms of area, delay, power in 90nm CMOS process technology. The result shows that proposed Square Root CSA structure is better in terms of area, power and Power Delay Product (PDP) than others.
References
- B. RamKumar and Harish M Kittur," Low-Power and Area- Efficient Carry Select Adder" IEEE Transactions on very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, February 2012
- A. Andamuthu and S. Rithanyaa ," Design of 128 bit Low Power and Area Efficient Carry Select Adder" International Journal of Advanced Research in Engineering (IJARE) Vol 1, Issue 1,2012 Page 31-34.
- Geetanjali Sharma, Uma Nirmal, Yogesh Mishra, "Comparative Analysis of High Performance Full Subtractor using Hybrid PTL/CMOS Logic" in proceeding of International Conference on Advances in Information Communication Technology and VLSI Design, Coimbatore, India, August 2010.
- Geetanjali Sharma, Uma Nirmal, Yogesh Mishra, "Synthesis of Hybrid PTL/CMOS Logic for Low Area/Power Applications" in proceeding of International Conference on System Dynamics and Control, India, August 2010.
- Shen-Fu Hsiao, Ming-Yu Tsai and Chia-Sheng Wen," Low Area/Power Synthesis using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-based Design Environment," IEEE Trans. Circuits and Systems vol. 57, NO. 1, Jan 2010.
- G. R. Cho and T. Chen, "Synthesis of Single/Dual-Rail Mixed PTL/Static Logic for Low-Power Applications," IEEE Trans. Computer-Aided Design Integration Circuits Syst. , vol. 23, no. 2, pp. 229–242, Feb. 2004.
- L. Suri, D. Lamba, K. Kritarth and G. Sharma, "High Performance and Power Efficient 32-bit carry select Adder using Hybrid PTL/CMOS Logic Style, " in IEEE International Multi Conference on Automation, Computing, Control, Communication and Compressed Sensing, Kerela, India, March 2013.
- K. Saranya, "Low Power and Area-Efficient Carry elect Adder," International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, January 2013.
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