The week's pick
Reseach Article
Shared Architecture for Encryption/Decryption of AES
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 69 - Number 18 |
| Year of Publication: 2013 |
| Authors: Richa Kumari Sharma, S. R. Biradar, B. P. Singh |
10.5120/12068-8067
|
Richa Kumari Sharma, S. R. Biradar, B. P. Singh . Shared Architecture for Encryption/Decryption of AES. International Journal of Computer Applications. 69, 18 ( May 2013), 1-6. DOI=10.5120/12068-8067
Abstract
Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. Here this paper presents the shared architectures for both encryption and decryption. Shared architecture reduces the area as well as the path delay. This methodology uses VHDL implementation of all the modules and results are concluded in terms of Delay and Frequency.
References
- Xinmiao Zhang and Keshab K. Parhi, "Implementation Approaches for the Advanced Encryption Standard Algorithm" IEEE 2002.
- Hui QIN, Tsutomu SASAO, Yukihiro IGUCHI, "An FPGA Design of AES Encryption Circuit with 128-bit Keys" GLSVLSI'05, ACM 2005
- Chih-Peng Fanand and Jun-Kui Hwang, "FPGA Implementations Of High Throughput Sequential And Fully Pipelined AES Algorithm" International journal of Electrical Engineering, vol. 15, no. 6, pp. 447-455, 2008.
- Mehran Mozaffari-Kermani and Arash Reyhani-Masoleh, "Efficient and High Performance Parallel Hardware Architecture for the AES-GCM" IEEE Transactions On Computers, vol. 61, no. 8, August 2012.
- Saambhavi Baskaran and Pachamuthu Rajalakshmi, "Hardware Software Co-Design of AES on FPGA" ICACCI '12,ACM August 2012.
- Ashwini M. Deshpande, Mangesh S. Deshpande and Devendra N. Kayatanavar, "FPGA Implementation of AES Encryption and Decryption" International Conference on Control, Automation, Communication and Energy conservation -2009
- X. Zhang and K. K. Parhi, "High-speed VLSI architectures for the AES algorithm" , IEEE Transactions on Very Large Scale Integration Systems, vol. 12, issue 9, pp. 95 967, Sep. 2004.
- Jin Gong ,Wenyi Liu, Huixin Zhang, "Multiple Lookup Table-Based AES Encryption Algorithm Implementation" Elseveir-2012 vol. 25 pg no. 842 – 847.
- Saurabh Kotiyal, Himanshu Thapliyal and Nagarajan Ranganathan, "Design of A Reversible Bidirectional Barrel Shifter" IEEE international conference 2011.
- J. Vijaya, M. Rajaram, "High Speed Pipelined AES with Mixcolum Transform "European Journal of Scientific Research" 2011. Vol. 61 No. 2 ,pp. 255-264.
- Douglas L. Perry, "VHDL: Programming by Example" McGraw-Hill Fourth Edition 2004.
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