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Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 70 - Number 11 |
| Year of Publication: 2013 |
| Authors: P. S. Aswale, S. S. Chopade |
10.5120/12005-6866
|
P. S. Aswale, S. S. Chopade . Comparative Study of Different Low Power Design Techniques for Reduction of Leakage Power in CMOS VLSI Circuits. International Journal of Computer Applications. 70, 11 ( May 2013), 16-24. DOI=10.5120/12005-6866
Abstract
Scaling of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. A chip's maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, standby leakage current becomes significant. As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analysis of inverter using conventional CMOS, stack and dual threshold transistor stacking, sleepy stack, sleepy keeper technique etc. The performance analyses of inverter were analyzed in 90nm technology using Virtuoso software (cadence). In order to reduce the static power dissipation, one has to sacrifice circuit performance and area. This paper presents the comparative study of all the approaches. The sleepy stack and variable body biasing approach shows improved results in terms of static power.
References
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