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Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 70 - Number 14 |
| Year of Publication: 2013 |
| Authors: Ashish Valuskar, Madhu Shandilya, Arvind Rajawat |
10.5120/12033-8078
|
Ashish Valuskar, Madhu Shandilya, Arvind Rajawat . Analysis of Mesh Topology of NoC for Blocking and Non-blocking Techniques. International Journal of Computer Applications. 70, 14 ( May 2013), 35-38. DOI=10.5120/12033-8078
Abstract
Network on Chip is efficient on-chip communication architecture for system on chip architectures. It enables the integration of a large number of computational and storage blocks on a single chip. The router is the basic element of NoC. The router architecture can be used for building a NoC with standard topology with low latency and high speed. In this paper, we implement and analyze a 3x3 mesh network configuration with routers which can support simultaneous routing requests, with blocking and non blocking inputs.
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