The week's pick
Reseach Article
A Novel Ripple/Carry Lookahead Hybrid Carry Select Adder Architecture
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 70 - Number 27 |
| Year of Publication: 2013 |
| Authors: Lakshmesha J, K. R. Usha Rani |
10.5120/12237-8416
|
Lakshmesha J, K. R. Usha Rani . A Novel Ripple/Carry Lookahead Hybrid Carry Select Adder Architecture. International Journal of Computer Applications. 70, 27 ( May 2013), 5-9. DOI=10.5120/12237-8416
Abstract
In this paper, two general architectures of Carry Select Adder (CSA) have been introduced for high speed addition. These CSA architectures utilize the hybridized structure of Carry Lookahead Adder (CLA) and Ripple Carry Adder (RCA). In these architectures the critical path delay has been reduced by reducing the number of multiplexer stages. The proposed designs are compared with regular CSA based on RCA. The second architecture showed 11. 3%, 3. 9% improvement in delay and an overhead of 13% in area.
References
- A. Weinberger and J. Smith, "A logic for high-speed addition," System Design of Digital Computer at the National Bureau of Standards: Methods for High-Speed Addition and Multiplication, National Bureau of Standards, circular 591, section 1, Feb. 1958, pp. 3–12.
- O J Bedrij, "Carry-Select Adder," IRE Trans. Electronic Computers, Vol. 11, pp. 340-346, 1962.
- R. E. Ladner, M. J. Fischer; 'Parallel Prefix Computation' JACM, 27(4):831-838, Oct. 1980.
- P. M. Kogge, H. S. Stone; 'A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations' IEEE Trans. , C-22(8):786-793, Aug. 1973
- T. Han, D. A. Carlson; 'Fast Area-Efficient VLSI Adders' 8th IEEE Symp. Computer Arithmetic, Como Italy, pp. 49-56, May 1987
- A. Tyagi, A reduced-area scheme for carry-select adders, IEEE Transactions on Computers 42 (10) (1993) 1163–1170.
- Yuke Wang, C. Pai, and Xiaoyu Song," The Design of Hybrid Carry-Lookahead/Carry–Select Adders", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 1, JANUARY 2002
- Y. Kim and L. S. Kim, "64-bit carry-select adder with reduced area," Electronics Letters, vol. 37, no. 10, pp. 614 – 615, May 2001.
- G. A. Ruiz, M. Granda, "An area-ef?cient static CMOS carry-select adder based on a compact carry look-ahead unit", Elsevier Microelectronics Journal (2004) 939–944.
- Yajuan He, Chip-Hong Chang and Jiangmin Gu," An Area Efficient 64-bit Square Root Carry-select Adder for Low Power Applications", IEEE, 2005.
- B. Ramkumar and Harish M Kittur. "Low-Power and Area-Ef?cient Carry Select Adder". IEEE Transaction on VLSI systems, 2011.
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