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Reseach Article

Reduced Complexity Hybrid Ripple Carry Lookahead Adder

by Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 70 - Number 28
Year of Publication: 2013
Authors: Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N
10.5120/12254-8202

Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N . Reduced Complexity Hybrid Ripple Carry Lookahead Adder. International Journal of Computer Applications. 70, 28 ( May 2013), 13-16. DOI=10.5120/12254-8202

@article{ 10.5120/12254-8202,
author = { Ravish Aradhya H. V, Lakshmesha J, Muralidhara K. N },
title = { Reduced Complexity Hybrid Ripple Carry Lookahead Adder },
journal = { International Journal of Computer Applications },
issue_date = { May 2013 },
volume = { 70 },
number = { 28 },
month = { May },
year = { 2013 },
issn = { 0975-8887 },
pages = { 13-16 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume70/number28/12254-8202/ },
doi = { 10.5120/12254-8202 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:34:04.474542+05:30
%A Ravish Aradhya H. V
%A Lakshmesha J
%A Muralidhara K. N
%T Reduced Complexity Hybrid Ripple Carry Lookahead Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 70
%N 28
%P 13-16
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper we discuss Hybrid Ripple Carry Lookahead Adder (HRCLA), which is a hybrid between Carry Lookahead Adder (CLA) and ripple adder (RA). In HRCLA time is traded off for area and power. HRCLA has been designed by rippling the last carry bit of a 4-bit CLA. HRCLA extracts the traits of Carry Lookahead Adders (CLA) speed and ripple adders (RA), area. A four bit proposed HRCLA has been implemented in Cadence using 45nm technology; the implementation results showed 12. 2 %Area, 4. 6 % power improvement and 14. 01 % critical path delay overhead over CLA.

References
  1. Wang Y, Pai C, Song X, "The design of hybrid carry look-ahead/carry-select adders, Circuits and Systems II," Analog and Digital Signal Processing, IEEE Transactions, Volume 49, 2002, pp: 16-24.
  2. A. Weinberger and J. L. Smith, "A Logic for High-Speed Addition," National Bureau of Standards, Circ. 591, 1958, pp: 3-12.
  3. Chen P, Zhao J, Xie G, Li Y, "An improved 32-bit carry-lookahead adder with Conditional Carry-Selection," 4th International Conference on Computer Science & Education, 2009, pp: 1911-1913.
  4. G. A. Ruiz, M. Granda, "An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit," Microelectronics Journal 35. 2004, pp: 939–944.
  5. V. Kantabruta, "A recursive carry-lookahead/carry-select hybrid adder," IEEE Transactions on Computers, 1993, pp: 1495–1499.
  6. C. Nagendra, M. J. Irwin, and R. M. Owens, "Area-time power tradeoffs in parallel adders," IEEE Transactions on Circuits and Systems II, 2002, vol. 43, pp: 689-702.
  7. N. Weste and K. Eshragian, "Principles of CMOS VLSI Designs: A System Perspective," 2nd ed. , Addison-Wesley, 2003.
  8. Kaushik Roy, Sharat Prasad, "Low-power CMOS VLSI Circuit Design," John Wiley, 2000.
  9. Phuong Thi Yen, Noor Faizah Zainul Abidin, Azrul Bin Ghazali, "Performance Analysis of Full Adder (Fa) Cells," IEEE Symposium on Computers & Informatics, 2011.
Index Terms

Computer Science
Information Sciences

Keywords

Ripple Adder Carry Lookahead Adder (CLA) Hybrid Ripple Carry Lookahead Adder (HRCLA)