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Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

by Leena Jain, Amarbir Singh
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 71 - Number 15
Year of Publication: 2013
Authors: Leena Jain, Amarbir Singh
10.5120/12433-8962

Leena Jain, Amarbir Singh . Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary. International Journal of Computer Applications. 71, 15 ( June 2013), 12-19. DOI=10.5120/12433-8962

@article{ 10.5120/12433-8962,
author = { Leena Jain, Amarbir Singh },
title = { Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 71 },
number = { 15 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 12-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume71/number15/12433-8962/ },
doi = { 10.5120/12433-8962 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:35:38.268434+05:30
%A Leena Jain
%A Amarbir Singh
%T Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary
%J International Journal of Computer Applications
%@ 0975-8887
%V 71
%N 15
%P 12-19
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Floorplan representation is a fundamental issue in designing a VLSI floorplanning algorithm as the representation has a great impact on the feasibility and complexity of floorplan designs. This survey paper gives an up-to-date account on various non-slicing floorplan representations in VLSI floorplanning.

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Index Terms

Computer Science
Information Sciences

Keywords

VLSI floorplanning non-slicing floorplan

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