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Reseach Article

High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications

by Zared Kamal, Qjidaa Hassan, Zouak Mohcine
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 71 - Number 18
Year of Publication: 2013
Authors: Zared Kamal, Qjidaa Hassan, Zouak Mohcine
10.5120/12584-9159

Zared Kamal, Qjidaa Hassan, Zouak Mohcine . High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications. International Journal of Computer Applications. 71, 18 ( June 2013), 7-16. DOI=10.5120/12584-9159

@article{ 10.5120/12584-9159,
author = { Zared Kamal, Qjidaa Hassan, Zouak Mohcine },
title = { High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 71 },
number = { 18 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 7-16 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume71/number18/12584-9159/ },
doi = { 10.5120/12584-9159 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:35:55.775318+05:30
%A Zared Kamal
%A Qjidaa Hassan
%A Zouak Mohcine
%T High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 71
%N 18
%P 7-16
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the Low dropout regulator. The proposed regulator LDO works with a supply voltage as low as 1. 8 V and provides a load current of 50 mA with a dropout voltage of 200 mV. It is designed in 0. 18 µm CMOS technology and the active area on chip measures 241×187 µm2. Simulation results show that the PSR of LDO is -60 dB at a frequency of 60 KHz and -41. 7 dB at a frequency of 1 MHz.

References
  1. G. A. Rinco-Mora and P. E Allen "Optimized frequency-Shaping Circuit Topologies for LDO's" IEEE trans. Circuits sys. II, Vol. 45, no. 6, Jun 1998, pp. 703-708.
  2. G. A. Rincon-Mora, "Active capacitor multiplier in miller-compensated circuits" IEEE J. Solid-State Circuits, Vol. 35, no. 1, pp. 26-32 Jan. 2000.
  3. Sai Kit Lau, Philip K. T. Mok and Ka Nang Leung "A Low-Dropout Regulator for SoC With Q-Reduction" IEEE Journal Of Solid-State Circuits,VOL. 42, NO. 3, MARCH 2007.
  4. Gabriel A. Rincon-Mora, Phillip E. Allen "A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator", IEEE Journal Of Solid-State Circuits,VOL. 33, NO. 1, JANUARY 1998.
  5. W. -J. Huang S. -I. Liu "Capacitor free low dorpout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array" IET Circuits Devices Syst. , 2008, Vol. 3, pp. 306-3016.
  6. Robert J. Milliken, Jose Silva-Martínez "Full On-Chip CMOS Low-Dropout Voltage Regulator," IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 54, No. 9, September 2007.
  7. Ma Haifeng, Zhou Feng "Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptative frequency compensation" Journal of Semiconductors, Vol. 31. No. 1 January 2010.
  8. C-C. Wang, C-C. Huang, and U. F. Chio "A linear LDO regulator with modified NMCF frequency compensation independent of off-chip capacitor and ESR" Analog Interg Circ Sig Process (2010) 63: 239-244.
  9. Gianluca Giustoli, Gaetano Palumbo, and Ester Spitale. "A 50 mA 1-nF Low Voltage Low –Dropout Voltage regulator for SoC Applications". ERTI journal, Vol. 32, Nunber 4, August 2010.
  10. K. N. Leung and P. K. T. Mok, "A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1691–1701, Oct. 2003.
  11. Ch. K. Chava, J. Silva-Martinez, " A Freqency Compensation Scheme fo LDO Voltage Regulators" IEEE Transactions on Circuits and Systems_I: Regular papers, VOL. 51, NO. 6, June 2004.
  12. C. -L. Chen W. -J. Huang and S. -I Liu "CMOS low dropout regulator with dynamic zero compensation" Electronics letrres 5 th July 2007 Vol. 43 No. 14.
  13. Gao Leisheng, Zhou Yumei, Wu Bin, and Jiang Jianhua. "A full on chip CMOS low dropout voltage regulator with VCCS compensation". Journal of Semiconductors, Vol. 31, No. 8 August 2010.
  14. Milliken, R. J. Silva-Martinez, J. , & Sanchez-Sinencio, E. (2009). " Full on-chip low-dropout voltage regulator. " IEEE Transactions on Circuits and System, 54(9), 1879–1890.
  15. H. Aminzadeh, R. Lotfi, and K. Mafinezhad " Area-Efficient Low-Cost Low-Dropout Regulators Using MOS Capacitors" IEEE 1-4244-2542-6/08/$20. 00. 2008.
  16. V. Majidzadeh, K. Mithat Silay, A. Schmid, C. Dehollain and Y. Leblebici "A fully on-chip LDO voltage regulator with 37 dB PSRR at 1 MHz for remotely powered biomedical implants" Analog Interg Circ Process (2011) 67: 158-168 DOI 10. 1007/s10470-010-9556-7.
  17. Q. Wu, W. Li, N. Li and J. Ren "A 1. 2 V 70 mA Low Drop-out Volyage Regulator in 0. 13 µm CMOS Process" IEEE (2011) 978-1-61284-193-9/11/$26. 00.
  18. Philip E. Allen, Douglas R. Holberg " CMOS Analog Circuit Dedign", second edition, 2002(OXFORD UNIVERSITY PRESS NEW YORK).
Index Terms

Computer Science
Information Sciences

Keywords

Low Dropout Regulator (LDO) MOSCAP NMCAC active feedback high PSR system on chip