CFP last date
22 April 2024
Reseach Article

FPGA Implementation of 3 bits BCH Error Correcting Codes

by Samir Jasam Mohammed, Hayder Fadhil Abdulsada
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 71 - Number 7
Year of Publication: 2013
Authors: Samir Jasam Mohammed, Hayder Fadhil Abdulsada
10.5120/12373-8698

Samir Jasam Mohammed, Hayder Fadhil Abdulsada . FPGA Implementation of 3 bits BCH Error Correcting Codes. International Journal of Computer Applications. 71, 7 ( June 2013), 35-42. DOI=10.5120/12373-8698

@article{ 10.5120/12373-8698,
author = { Samir Jasam Mohammed, Hayder Fadhil Abdulsada },
title = { FPGA Implementation of 3 bits BCH Error Correcting Codes },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 71 },
number = { 7 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 35-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume71/number7/12373-8698/ },
doi = { 10.5120/12373-8698 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:34:55.979001+05:30
%A Samir Jasam Mohammed
%A Hayder Fadhil Abdulsada
%T FPGA Implementation of 3 bits BCH Error Correcting Codes
%J International Journal of Computer Applications
%@ 0975-8887
%V 71
%N 7
%P 35-42
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper describes the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) code using a Field Programmable Gate Array (FPGA) reconfigurable chip. BCH code is one of the most important cyclic block codes. Designing on FPGA leads to a high calculation rate using parallelization (implementation is very fast), and it is easy to modify. BCH encoder and decoder have been designed and simulated using MATLAB, Xilinx-ISE 10. 1 Web PACK and implemented in a xc3s700a-4fg484 FPGA. In this implementation we used 15 bit-size code word and 5 bits data, any 3 bits error in any position of 15 bits has been corrected. The results show that the system works quite well.

References
  1. Neubauer, J. Freudenberger and V. Kuhn "Coding Theory Algorithms, Architectures and Applications" John Wiley & Sons, 2007.
  2. T. K. Moon, "Error Correction Coding", John Wiley & Sons, 2005.
  3. A. S. Das, S. Das, and J. Bhaumik "Design of RS (255,251) Encoder and Decoder in FPGA", international journal of soft computing and engineering, Volume- 2, Issue-6, January 2013.
  4. J. G. Proakis, "Digital Communications", Prentice-Hall, 4th edition, 2005.
  5. S. Lin, and D. J. Costello Jr. "Error Control Coding Fundamentals and Applications", Prentice-Hall, New Jersey, 1983.
  6. R. Merha, G. Saini, and S. Singh, "FPGA Based High Speed BCH Encode for Wireless communication Applications", International Conference on Communication System and Network Technologies, 2011.
  7. B. Sklar, "Digital Communications Fundamentals and Applications Mathematical Methods and Algorithms", Prentice Hall, 2nd edition, 2001.
  8. Y. Jiang, "A Practical Guide to Error-Control Coding Using MATLAB", 2010.
  9. L. M. Ionescu, C. Anton, and I. Tutanescu, "Hardware Implementation of BCH Error- Correcting Codes on FPGA", Intrnational Journal of Intelligent Computing Research, Volume 1, Issue 3, June 2010.
  10. S. J. Mohammed, H. F. Abdulsada, "Design and Implementation of 2 BCH Error Correcting Codes using FPGA", Journal of Telecommunicatios, Volume 19, ISSUE 2, APRIL 2013.
  11. I. Kuon, R. Tessier and J. Rose. " FPGA Architecture: Survey and Challenges", 2008.
  12. J. P. Deschamps, G. J. A. Bioul and G. D. Sutter, "Synthesis of Arithmetic Circuits FPGA, ASIC and Embadded Systems", John Wiley & Sons, 2006.
  13. A. K. Maini, " Digital Electronics Principles, Devices and Applications ", John Wiley & Sons, 2007.
  14. R. Woods, J. McAllister, G. Lightbody and Y. Yi, "FPGA-based Implementation of Signal Processing Systems", John Wiley & Sons, 2008.
Index Terms

Computer Science
Information Sciences

Keywords

Error correcting codes BCH codes encoding decoding FPGA