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Improved Fault Tolerant Sparse KOGGE Stone ADDER

by Mangesh B Kondalkar, Arunkumar P Chavan, P Narashimaraja
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 75 - Number 10
Year of Publication: 2013
Authors: Mangesh B Kondalkar, Arunkumar P Chavan, P Narashimaraja
10.5120/13150-0582

Mangesh B Kondalkar, Arunkumar P Chavan, P Narashimaraja . Improved Fault Tolerant Sparse KOGGE Stone ADDER. International Journal of Computer Applications. 75, 10 ( August 2013), 36-41. DOI=10.5120/13150-0582

@article{ 10.5120/13150-0582,
author = { Mangesh B Kondalkar, Arunkumar P Chavan, P Narashimaraja },
title = { Improved Fault Tolerant Sparse KOGGE Stone ADDER },
journal = { International Journal of Computer Applications },
issue_date = { August 2013 },
volume = { 75 },
number = { 10 },
month = { August },
year = { 2013 },
issn = { 0975-8887 },
pages = { 36-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume75/number10/13150-0582/ },
doi = { 10.5120/13150-0582 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:43:57.336262+05:30
%A Mangesh B Kondalkar
%A Arunkumar P Chavan
%A P Narashimaraja
%T Improved Fault Tolerant Sparse KOGGE Stone ADDER
%J International Journal of Computer Applications
%@ 0975-8887
%V 75
%N 10
%P 36-41
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A fault tolerant adder implemented using Kogge-stone configuration can correct the error due to inherent redundancy in the carry tree but no error detection is possible. This proposed design is based on fault tolerant adder [1] that uses Sparse kogge-stone adder that is capable of both fault detection and correction. Fault tolerance is achieved by using two additional ripple carry adders that form the basis of triple mode redundancy adder. Triple mode redundancy is one of the most common methods used to create fault tolerant designs in both ASIC and FPGA implementations. The latency will be increased because of the voter in the circuit's critical path. More advanced fault tolerant methods exist including roving and graceful degradation approaches. Allowing fault tolerance to operate at different levels of abstraction might facilitate a more cost-effective design. Several enhancements are introduced in the design; the error recovery time is reduced by using a 16-bit register, error correction due to fault in multiple ripple carry adders is included which improves the reliability of the circuit. The power analysis and the timing analysis for the estimation of setup time and hold time is also performed.

References
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Index Terms

Computer Science
Information Sciences

Keywords

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