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Implementation of an Efficient Multiplier Architecture over a Conventional Methods using Ancient Indian Vedic Sutra
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 75 - Number 15 |
| Year of Publication: 2013 |
| Authors: Bhushan M. Shelke, Shubhangi A. Wakode |
10.5120/13191-0860
|
Bhushan M. Shelke, Shubhangi A. Wakode . Implementation of an Efficient Multiplier Architecture over a Conventional Methods using Ancient Indian Vedic Sutra. International Journal of Computer Applications. 75, 15 ( August 2013), 50-56. DOI=10.5120/13191-0860
Abstract
Fast multiplication is very important in processing of digital signals like DSP for convolution, Fourier Transform, etc. Many conventional methods are used for designing a multiplier for processing a digital signal. In this paper, A fast method for multiplication based on Ancient Indian Vedic mathematics is proposed. The whole of Vedic mathematics is based on 16 sutras (formulae). Among the various methods of multiplication in Vedicmathematics, Urdhava Tiryakbhyam (Vertically and Crosswise) is discussed in detail. This is the general multiplication formula applicable to all cases of multiplication. For implimentation of a efficient Architecture simple Boolean logic is combined with Vedic formulas, which reduces the partial products and sums generated in one step. The coding is done in VHDL and synthesis is done using Xilinx ISE 9. 1i simulator. Results are compaired with several conventional techniques.
References
- Vedic mathematics or sixteen simple mathematical formulae from the Vedas by Jagadguru Swami Shri Bharati Krishna Tirthaji Maharaja, General Editor – Dr. V. S. Agrawal , First Edition : Varanasi ,1965.
- Kabiraj Sethi , Rutuparna Panda : "An Improved Squaring Circuit for Binary Numbers", (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 3, No. 2, 2012.
- G. Ganesh Kumar, V. Charishma : "Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques", International Journal of Scientific and Research Publications, Volume 2, Issue 3, March 2012 ISSN 2250-3153.
- P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya :" Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors", international journal on smart sensing and intelligent systems vol. 4,No. 2 june 2011.
- S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur, Girish V A : "Implementation of Vedic Multiplier for Digital Signal Processing", International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011 Proceedings published by International Journal of Computer Applications® (IJCA).
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