The week's pick
Reseach Article
An Efficient Low Power Viterbi Decoder Design using T-algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 76 - Number 5 |
| Year of Publication: 2013 |
| Authors: K. Sridhar Reddy, M. Nagarjuna, H. Shravan Kumar |
10.5120/13246-0707
|
K. Sridhar Reddy, M. Nagarjuna, H. Shravan Kumar . An Efficient Low Power Viterbi Decoder Design using T-algorithm. International Journal of Computer Applications. 76, 5 ( August 2013), 34-39. DOI=10.5120/13246-0707
Abstract
This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. It implements the viterbi decoder using T-algorithm for decoding a bit-stream encoded by a corresponding forward error correction convolutional encoding system. A lot of digital communication systems incorporated a viterbi decoder for decoding convolutionally encoded data. The viterbi decoder is able to correct errors in received data caused by channel noise. We proposed an architecture implementing a Viterbi Decoder with T-algorithm deployed with threshold generator unit and purge unit to reduce the number of states which reduce power consumption. We propose modified architecture for the survivor Metric Unit to reduce the memory Access power during the trace back operation. The proposed viterbi decoder is carried out for rate-1/2 with a standard constraint length 7. The Synthesis results will be done using cadence RTL Encounter Tool. For ASIC synthesis, we use TSMC 45-nm CMOS Process. The architecture which reduces the complexity and power Consumption by as much as 70% without effecting the decoding speed.
References
- "High Speed Low-Power Viterbi Decoder Design for TCM Decoder", IEEE Transaction on VLSI, VOL. 20, NO. 4, APRIL 2012.
- "Bandwidth-efficient modulations," Consultative Committee For Space Data System, Matera, Italy, CCSDS 401(3. 3. 6) Green Book, Issue 1, Apr. 2003.
- J. B. Anderson and E. Offer, "Reduced-state sequence detection with convolutional codes," IEEE Trans. Inf. Theory, vol. 40, no. 3, pp. 965–972, May 1994.
- C. F. Lin and J. B. Anderson, "T-algorithm decoding of channel convolutional codes," presented at the Princeton Conf. Info. Sci. Syst. , Princeton, NJ, Mar. 1986.
- S. J. Simmons, "Breadth-first trellis decoding with adaptive effort, "IEEE Trans. Commun. , vol. 38, no. 1, pp. 3–12, Jan. 1990.
- F. Chan and D. Haccoun, "Adaptive viterbi decoding of convolutional codes over memory-less channels," IEEE Trans. Commun. , vol. 45, no. 11, pp. 1389–1400, Nov. 1997.
- R. A. Abdallah and N. R. Shanbhag, "Error-resilient low-power viterbi decoder architectures," IEEE Trans. Signal Process. , vol. 57, no. 12, pp. 4906–4917, Dec. 2009
- J. Jin and C. -Y. Tsui, "Low-power limited-search parallel state viterbi decoder implementation based on scarece state transition," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 15, no. 11, pp. 1172–1176,Oct. 2007.
- F. Sun and T. Zhang, "Low-power state-parallel relaxed adaptive viterbi decoder design and implementation," in Proc. IEEE ISCAS, May 2006, pp. 4811–4814.
- J. He, H. Liu, and Z. Wang, "A fast ACSU architecture for viterbi decoder using T-algorithm," in Proc. 43rd IEEE Asilomar Conf. Signals,Syst. Comput. , Nov. 2009, pp. 231–235.
- J. He, Z. Wang, and H. Liu, "An efficient 4-D 8PSK TCM decoder architecture," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 18, no. 5, pp. 808–817, May-2010.
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