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A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 77 - Number 5
Year of Publication: 2013
E. Konguvel
J. Raja
M. Kannan

E Konguvel, J Raja and M Kannan. Article: A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme. International Journal of Computer Applications 77(5):9-15, September 2013. Full text available. BibTeX

	author = {E. Konguvel and J. Raja and M. Kannan},
	title = {Article: A Low Power VLSI Implementation of 2X2 MIMO OFDM Transceiver with ICI-SC Scheme},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {77},
	number = {5},
	pages = {9-15},
	month = {September},
	note = {Full text available}


This paper presents a VLSI implementation of 2X2 MIMO OFDM transceiver with self ICI cancellation scheme at very low power. Phase noise and the carrier frequency offset (CFO) are the major problems in Orthogonal Frequency Division Multiplexing (OFDM) that destroys the mutual orthogonality of the sub-carriers over a given time interval. This non-orthogonality between the sub-carriers causes Inter-Carrier Interference (ICI). Interference among the sub-carriers degrades the performance of the system greatly. In the proposed scheme, the space coding is applied over two successive OFDM symbols and neighboring subcarriers simultaneously within single symbol duration. This reduces the delay encountered in space coding and decoding since no OFDM symbol has to be buffered. This leads to the self-cancellation of ICI components in the desired signal. The effects of Phase Noise and CFO in MIMO OFDM are greatly reduced by the space frequency block codes. Matlab simulations are performed prior to the Verilog HDL coding for functional verification. The SFBC coded MIMO OFDM transceiver is designed, implemented and tested in TSMC 180nm technology using Cadence NC Simulator, RTL Compiler and Altera ModelSim with DE2 EP2C35F672C6. The proposed 2X2 MIMO OFDM transceiver with ICI-SC technique has 41,298 numbers in logic gates and consumes 17. 92mw in power dissipation at a maximum throughput of 1. 13Gbps.


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