Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

Analysis of a Third-Order Charge-Pump Phase-Locked Loops used for Wireless Sensor Transceiver

Print
PDF
International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 77 - Number 5
Year of Publication: 2013
Authors:
Intissar Toihria
Rim Ayadi
Mohamed Masmoudi
10.5120/13394-1036

Intissar Toihria, Rim Ayadi and Mohamed Masmoudi. Article: Analysis of a Third-Order Charge-Pump Phase-Locked Loops used for Wireless Sensor Transceiver. International Journal of Computer Applications 77(5):36-41, September 2013. Full text available. BibTeX

@article{key:article,
	author = {Intissar Toihria and Rim Ayadi and Mohamed Masmoudi},
	title = {Article: Analysis of a Third-Order Charge-Pump Phase-Locked Loops used for Wireless Sensor Transceiver},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {77},
	number = {5},
	pages = {36-41},
	month = {September},
	note = {Full text available}
}

Abstract

The evaluation of integrated circuits such as Phase Locked Loops is a challenge in mixed-signal design. In most cases, these circuits are evaluated with electrical stimulations. To verify the proper operation of system before moving on to the design process, it is necessary to model these performances parameters with a hardware description language. At behavioral level, the performances of circuits are optimized without considering its transistor level structure. This paper, present an exact s-domain model analysis of a Third-Order Charge-Pump Phase-Locked Loops (CP-PLLs) used for wireless sensor transceiver using state equations of Phase Frequency Detector. Both the state equations and the transfer functions behavior modeling are described using this analysis. The linear state equations and s-domain transfer functions are provided. Critical advantage of illustrated methodology is a shortened PLL operating process due to the use of fast-simulating models at behavioral level. The analysis is verified using behavioral simulations with VHDL-AMS in Simplorer.

References

  • I. Young, J. Greason, and K. Wong, ''PLL clock generator with 5 to 10MHz of lock range for microprocessors'', IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
  • M. Meghelli, B. Parker, H. Ainspan, and M. Soyuer, ''SiGe BiCMOS 3. 3-V clock and data recovery circuits for 10-Gb/s serial transmission systems,'' IEEE J. Solid-State Circuits, vol. 35, pp. 1992-1995, Dec. 2000.
  • H. Rategh, H. Samavati, and T. Lee, ''A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LNA receiver,'' IEEE J. Solid-State Circuits, vol. 35, pp. 780-787, May. 2000.
  • C. Munker, B. -U. Klepser, B. Neurauter, and C. Mayer, Digital RF CMOS transceivers for GPRS and EDGE, in IEEE Radio Frequency Integrated Circuits (RFIC) Symp. Dig. of Papers, 2005, pp. 265–268.
  • J. Hein and J. Scott, ''z-domain model for discrete-time PLLs,'' IEEE Trans. Circuits Syst, vol. 35, pp. 1393-1400, Nov. 1998.
  • F. M. Gardner, Charge-Pump Phase-Lock Loops, IEEE Trans. Communication, vol. COM-28, 1849–1858, Nov. 1980.
  • I. Novof, J. Austin, R. Kelkar, D. Strayer, and S. W Syatt, ''Fully inte-grated CMOS phase-locked loop with 15 to 240MHZ locking range and 50ps jitter,'' IEEE J. Solid-State Circuits, Vol. 30, pp. 1259-1266; Nov. 1995.
  • J. Maneatis, ''Low-jitter process-independent DLL and PLL based on self-biased techniques,'' IEEE J. Solid-State Circuits, Vol. 31, pp. 1723-1732; Nov. 1996.
  • Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, and Un-Ku Moon, ''Analysis of Charge Pump Phase Locked Loops'', IEEE Transactions on circuits and systems, Vol. 51, No. 9; September. 2004.
  • Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, and Kartikeya Mayaram,'' Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy;'' IEEE Transactions on circuits and systems, II: Express Briefs, Vol. 54, No. 3, March. 2007.
  • B Razavi, Monolithic, Phase-Locked Loops and Clock Recovery Circuits; Theory and Design, IEEE Press 1996.
  • Intissar Toihria, Rim Ayadi and Mohamed Masmoudi, An Effective CMOS Charge Pump-Phase Frequency Detector Circuit for PLLs Applications, International Multi-Conference on Systems, Signals & Devices (SSD) Hammamet, Tunisia, March 18-21, 2013.
  • Intissar Toihria, Rim Ayadi and Mohamed Masmoudi, Design of an Effective Charge Pump-Phase Locked Loops Architecture for RF Applications, International Journal of Computer Applications, Volume 74– No. 3, July 2013.
  • F. M. Gardner, Phase Lock Techniques, 2nd ed. , New York, Wiley, 1979.
  • Deng Wen-Juan, Liu Shubo, Wang Song, Chen Jian, Zou Jijun, On The Design Of The Charge Pump PLL In Video Decoder, Journal of Theoretical and Applied Information Technology, 15th October 2012. Vol. 44 No. 1
  • Debashis Mandal and T. K. Bhattacharyya, Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design, Journal of Computers, VOL. 3, NO. 4, Avril 2008.
  • K. Holladay, Design a PLL for specific loop bandwidth, END EUROPE, pp 64-66, October 2000.
  • A Novel Built-In Self-Test Architecture for Charge-Pump Phase Locked Loops. J. Ramesh and K. Gunavathi. ICGST-PDCS Journal, Volume 7, Issue 1, May, 2007
  • Retdian, N. , Takagi, S. and Fujii, N. , "Voltage controlled ring oscillator with wide tuning range and fast voltage swing", IEEE Asia-Pacific Conference, ASIC on 2002. Proceedings, pp 201 – 204, Aug. 2002.
  • J. -J. Charlot, N. Milet-Lewis, T. Zimmer and H. Lévi (BEAMS Association). VHDL-AMS for mixed technology and mixed signal, an overview.