CFP last date
20 May 2024
Reseach Article

High Performance and Function Design on the Transistor Level

by Tripti Sharma, K. G. Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 78 - Number 10
Year of Publication: 2013
Authors: Tripti Sharma, K. G. Sharma
10.5120/13528-1259

Tripti Sharma, K. G. Sharma . High Performance and Function Design on the Transistor Level. International Journal of Computer Applications. 78, 10 ( September 2013), 33-35. DOI=10.5120/13528-1259

@article{ 10.5120/13528-1259,
author = { Tripti Sharma, K. G. Sharma },
title = { High Performance and Function Design on the Transistor Level },
journal = { International Journal of Computer Applications },
issue_date = { September 2013 },
volume = { 78 },
number = { 10 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = { 33-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume78/number10/13528-1259/ },
doi = { 10.5120/13528-1259 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:51:14.666526+05:30
%A Tripti Sharma
%A K. G. Sharma
%T High Performance and Function Design on the Transistor Level
%J International Journal of Computer Applications
%@ 0975-8887
%V 78
%N 10
%P 33-35
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper proposes a new design of pass transistor logic based 2T AND gate. Performance comparison of proposed gate with traditional CMOS, complementary pass-transistor logic design and GDI techniques is presented. Different methods have been compared with respect to the number of devices, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing ones. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology.

References
  1. N. Weste and K. Eshraghian, Principles of CMOS digital design. Reading, MA: Addison-Wesley, 304–307.
  2. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, 1992 "Low- power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, (Apr. 1992), 473–484.
  3. A. P. Chandrakasan and R. W. Brodersen, 1995, Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, (Apr. 1995), 498–523 Apr. 1995.
  4. W. Al-Assadi, A. P. Jayasumana, and Y. K. Malaiya, 1991, "Pass-transistor logic design," Int. J. Electron. , vol. 70, 739–749.
  5. K. Yano, Y. Sasaki, K. Rikino, and K. Seki, 1996, "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, vol. 31, (June 1996), 792–803.
  6. R. Zimmermann and W. Fichtner, 1997, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, (June 1997), 1079–1090.
  7. J. P. Uyemura, 1992, Circuit Design for CMOS VLSI. Norwell, MA: Kluwer Academic, 88–129.
  8. S. Veeramachaneni, M. B. Srinivas, 2008, "New Improved 1-Bit Full Adder Cells," CCECE/ CCGEI, Niagara Falls. Canada, (May 5-7 2008), 735.
  9. D. Wang, M. Yang, W. Cheng, X. Guan, Z. Zhu, Y. Yang, 2009, "Novel Low Power Full Adder Cells in 180nm CMOS Technology," in Prod. IEEE ICIEA, 430.
  10. P. M. Lee, C. H. Hsu, Y. H. Hung, 2007, "Novel 10-T Full Adder realized by GDI Structure", IEEE international symposium on integrated circuits (ISIC-2007), 115-118.
  11. Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, 2002, "Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits," IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 10, No. 5, (Oct. 2002), 566-581.
  12. Sung-Mo Kang, Yusuf Leblebici, 2003, Analysis and Design for CMOS Digital Integrated Circuits, 127,481-492.
Index Terms

Computer Science
Information Sciences

Keywords

AND gate PTL and Power-delay product.