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Implementation of RS Encoder and RS Decoder using UHD Architecture
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 78 - Number 12 |
| Year of Publication: 2013 |
| Authors: Naresh. B, S. Srinivas |
10.5120/13575-1308
|
Naresh. B, S. Srinivas . Implementation of RS Encoder and RS Decoder using UHD Architecture. International Journal of Computer Applications. 78, 12 ( September 2013), 17-23. DOI=10.5120/13575-1308
Abstract
Reed Solomon (RS) codes are a sort of non-binary cyclic codes. This code is widely used in wireless and mobile communication units. RS encoder along with RS decoder using UHD architecture is designed in this paper. In this brief, a novel low complexity reformulated inverse-free burst-error correction algorithm is developed. Then based on the Proposed RiBC algorithm, a Unified VLSI architecture is designed. It will be shown that, it can achieve high-speed, throughput and improved error correcting capability than Hard Decision Decoding (HDD) design with less area. A design of (7, 3) Reed Solomon encoder and Decoder are implemented using Verilog hardware description language (HDL) code, simulated and synthesized by XILINX ISE simulator.
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