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Performance Improvement of GFCAL Circuits
by
Shipra Upadhyay,
R. K. Nagaria,
R. A. Mishra
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 78 - Number 5 |
| Year of Publication: 2013 |
| Authors: Shipra Upadhyay, R. K. Nagaria, R. A. Mishra |
10.5120/13487-1193
|
Shipra Upadhyay, R. K. Nagaria, R. A. Mishra . Performance Improvement of GFCAL Circuits. International Journal of Computer Applications. 78, 5 ( September 2013), 29-37. DOI=10.5120/13487-1193
@article{
10.5120/13487-1193,
author = {
Shipra Upadhyay,
R. K. Nagaria,
R. A. Mishra
},
title = { Performance Improvement of GFCAL Circuits },
journal = {
International Journal of Computer Applications
},
issue_date = { September 2013 },
volume = { 78 },
number = { 5 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = {
29-37
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume78/number5/13487-1193/
},
doi = { 10.5120/13487-1193 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:50:50.211207+05:30
%A Shipra Upadhyay
%A R. K. Nagaria
%A R. A. Mishra
%T Performance Improvement of GFCAL Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 78
%N 5
%P 29-37
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this paper authors have presented a new approach to improve the performance of the glitch free cascadable adiabatic logic (GFCAL) circuit by replacing the triangular power supply with sinusoidal and trapezoidal power supplies (that control the charging and discharging of the capacitive load) and by sizing of transistors. A simulative investigation and performance analysis of proposed approach based 3 bit GFCAL counter, GFCAL JK flip flop and GFCAL 6T-SRAM circuit have also been done. The triangular power supply produces very large delay at the outputs of GFCAL circuits thus it will be very difficult to cascade larger circuits. A solution to provide cascadability is optimization of the delay. In the proposed approach the delay of GFCAL counter for triangular supply has been improved about 40% and 60% whereas for JK flip flop it is 46% and 49% and for 6T SRAM it is 17% and 91% with sinusoidal and trapezoidal power clocks respectively.
References
- Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwati,"New Design Methodologies for High Speed Mixed- Mode Full Adder Circuit", International Journal of VLSI and Communication Systems (VLSICS), AIRCC Publication, 2(2), 2011, 78-98,2011.
- Adarsh Kumar Agarwal, S. Wairya, R. K. Nagaria and S. Tiwari, "A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits", World Applied Science Journal (WASJ),Special Issue of Computer & IT, 7, 2009, 138-144.
- D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2003.
- N. H. E. Weste and D. Harris, CMOS VLSI Design–A Circuits and Systems Perspective, 3rd ed. Reading, MA: Addison-Wesley, 2004.
- Vivek K. De and James D. Meindl, "Opportunities for non-Dissipative Computation", in, IEEE Conf. , 1995, 297–300.
- W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y. -C. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Trans. VLSI Syst. , 2, Dec. 1994, 398–407.
- Y. Moon and D. -K. Jeong, "An efficient charge recovery logic circuit," IEEE J. Solid-State Circuits, 31(4), Apr. 1996, 514–522.
- Yibin Ye, And Kaushik Roy , "QSERL: Quasi-static Energy Recovery Logic", IEEE Journal Of Solid-state Circuits,36(2), Feb 2001, 239-248.
- Cihun-siyong Alex Gong, Muh- Tihan Shiue, Ci-Tong Hong, And Kai- Wen Yao, "Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0. 18-?m CMOS", IEEE Transactions On Circuits and Systms- I: Regular Papers, 55(9),Oct 2008, 2595-2607.
- N. S. S. Reddy, M. Satyam,and K. L. Kishore, "Cascadable Adiabatic Logic Circuits for Low-Power Applications", IET Circuits Devices Syst. , 2(6), Jun 2008, 518–526.
- Nazarul Anuar, yashuhiro Takahashi, and Toshikazu Sekine, "LSI implementation of a low-power 4x4-bit array two-phase clocked adiabatic static CMOS logic multiplier",Microelectronics Journal, Elsevier, 43, 2012, 244-249.
- Shipra Upadhyay, R. A. Mishra, R. K. Nagaria and S. P. Singh, "DFAL: Diode Free Adiabatic Logic Circuits", International Scholarly Research Network: ISRN Electronics, Hindawi, 2013, 1-12.
- Sompong Wisetphanichkij, Kobchai Dejhan, "The Combinational and Sequential Adiabatic Circuit Design and Its Applications", Circuits Syst Signal Process , 28,2009, 523–534.
- Conrad H. Ziesler, and Marios C. Papaefthymiou, "A True Single-Phase Energy-Recovery Multiplier",Suhwan Kim, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(2),Apr 2003,. 52-63.
- Mehrdad Khatir, Alireza Ejlali, Amir Moradi,"Improving The Energy Efficiency of Reversible Logic Circuits by The Combined Use of Adiabatic Styles", Integration the VLSI Journal, Elsevier, 44, 2011, 12-21.
- Visvesh S. Sathe, Juang-ying Chueh, and Marios C. Papefthymiou,"Energy Efficient GHz-Class Charge Recovery Logic", IEEE Journal of Solid-state Circuits, 42(1), Jan 2007,38-47.
- Myeong-Eun Hwang, Arijit Raychowdhury, and Kaushik Roy,"Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies", IEEE Transactions on Circuits and Systems—i: regular Papers, 52(8), 2005, 1580-1589.
- A. G. Dickinson and J. S. Denker, "Adiabatic dynamic logic," IEEE Journal of Solid-State Circuits, 30(3), 1995,311–314.
- K. W. Ng, K. A. Ng, K. T. Lau, "Energy-recovery flip-flop design using improved adiabatic pseudo-domino logic structure", Microelectronics Journal, Elsevier, 30, 1999, 851–854.
- Jouko Marjonen and Markku A. Berg, "A Single Clocked Adiabatic Static Logic—A Proposal for Digital Low Power Applications", Journal of VLSI Signal Processing, Kluwer Academic Publishers, 27, 2001, 253–268.
- V. I. Starosel'skii, "Adiabatic Logic Circuits: A Review", Russian Microelectronics, vol. 31, no. 1, pp. 37–58, translated from Mikroelektronika, 31(1), 2002, 42–65.
- V. V. Losev and V. I. Starosel'skii, "Power Consumption of Asymptotically Adiabatic Static Logic Gates", Russian Microelectronics, vol. 33, no. 3, 2004, pp. 188–194, translated from Mikroelektronika, 33(3),2004, 233–239.
- Peng-jun WANG, Jian XU, Shi-yan YING, "Design of adiabatic two's complement multiplier-accumulator based on CTGAL", Journal of Zhejiang University SCIENCE A, Springer, 10(2),2009, 172-178.
- Jianping Hu, Dong Zhou, Ling Wang, Huiying Dong, "Low-power interface circuits between adiabatic and standard CMOS circuits", Analog Integrated Circuits and Signal Processing, Springer, 60, 2009,105–115.
- Wang Pengjun and Yu Junjun, "Design of Two-Phase Sinusoidal Power Clock and Clocked Transmission Gate Adiabatic Logic Circuit", Journal of Electronics (China), 24(2),2007, 225-231.
- A. Blotti, R. Saletti, "Ultralow-power adiabatic circuit semi-custom design", IEEE Transaction on VLSI Systems, 12(11), 2004, 1248–1253.
- Y. Wu, H. Dong, Y. Wang, and J. Hu, "Low-power adiabatic sequential circuits using two-phase power-clock supply," in ASIC, 2005. ASICON 2005. 6th International Conference on ASIC proceedings, 1, 2005, 235 –238.
- Shipra Upadhyay, R. K. Nagaria and R. A. Mishra,"Complementary Energy Path Adiabatic Logic based Full Adder Circuit",A Journal of World Academy of Science Engineering & Technology, 66, 2012, 161-167.
- Shipra Upadhyay, R. K. Nagaria, R. A. Mishra, S. P. Singh and Amit Shukla, Triangular Power Supply Based Adiabatic Logic Circuits, World Applied Sciences Journal (WASJ), (accepted).
Index Terms
Computer Science
Information Sciences
Keywords