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Threshold Voltage Control through Multiple Supply for Low Power IG-FinFET Circuit

by Manorama, Pavan Shrivastava, Saurabh Khandelwal, Shyam Akashe
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 78 - Number 8
Year of Publication: 2013
Authors: Manorama, Pavan Shrivastava, Saurabh Khandelwal, Shyam Akashe
10.5120/13508-1261

Manorama, Pavan Shrivastava, Saurabh Khandelwal, Shyam Akashe . Threshold Voltage Control through Multiple Supply for Low Power IG-FinFET Circuit. International Journal of Computer Applications. 78, 8 ( September 2013), 11-15. DOI=10.5120/13508-1261

@article{ 10.5120/13508-1261,
author = { Manorama, Pavan Shrivastava, Saurabh Khandelwal, Shyam Akashe },
title = { Threshold Voltage Control through Multiple Supply for Low Power IG-FinFET Circuit },
journal = { International Journal of Computer Applications },
issue_date = { September 2013 },
volume = { 78 },
number = { 8 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = { 11-15 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume78/number8/13508-1261/ },
doi = { 10.5120/13508-1261 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:51:03.308742+05:30
%A Manorama
%A Pavan Shrivastava
%A Saurabh Khandelwal
%A Shyam Akashe
%T Threshold Voltage Control through Multiple Supply for Low Power IG-FinFET Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 78
%N 8
%P 11-15
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

As scale down the standard single-gate bulk MOSFET dimensions, vast challenges in the nanometer regime due to the brutal short-channel effects arises that grounds an exponential increases in the leakage current, power consumption and enriched the sensitivity in process variations. Double gate and multi-gate technology alleviate these restrictions by producing a stronger control over a thin silicon body with electrically coupled gates. In this paper, proposed a methodology for independent gate (IG) FinFET Nand circuit in which applies multiple supplies for controlling the threshold voltage V_thby which IG FinFET can improve the speed, saving the power and minimize the area of the circuit by 23-25%. The most advantageous IG keeper gate bias conditions are identified for reaching maximum savings (approx 40-43%) in delay and power (24-28%) while maintaining identical noise immunity as compared to the simple supply IG-FinFET domino circuits. Here the circuit efficiency also enhances.

References
  1. Sherif A. Tawfik and Volkan Kursun, "Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs", JANUARY 2008,IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 1.
  2. Anish Muttreja, Prateek Mishra and Niraj K. Jha, "Threshold Voltage Control through Multiple Supply Voltages for Power-efficient FinFET Interconnects", 2008, 21st International Conference on VLSI Design, IEEE.
  3. B. Swahn and S. Hassoun. Gate sizing: FinFETs vs 32nm bulk MOSFETs. July 2006, In Proc. Design Automation Conf. , pages 528–531.
  4. J. Colinge, FinFETs and other multi-gate transistors. Springer, Nov. 2007.
  5. D. Hisamoto, L. Wen-Chin, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, K. Tsu-Jae, J. Bokor, and H. Chenming, (2000) "FinFET – a self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, pp. 2320-2325.
  6. Masoud Rostami and Kartik Mohanram "Novel dual-Vth independent-gate FinFET circuits" 2010, Digital Object Identifier: 10. 1109/ASPDAC. 2010. 5419680, Page(s): 867 – 872.
  7. Muttreja, N. Agarwal, and N. K. Jha, "CMOS logic design with independent gate FinFETs," 2007, in Proc. Int. Conf. Computer Design, Oct. , pp. 560–567.
  8. K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami, "Automated low-power technique exploiting multiple supply voltages applied to a media processor," Mar. 1998, IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 463–472.
  9. K. Roy, L. Wei, and Z. Chen, "Multiple-Vdd and multiple-Vth CMOS (MVCMOS) for low-power applications," in Proc. Int. Symp. Computer Architecture, Oct. 1999, pp. 366–370.
  10. V Narendar, Wanjul Dattatray R, Sanjeev Rai and R. A. Mishra, "Design of High-performance Digital Logic Circuits based on FinFET Technology", March 2012, International Journal of Computer Applications (0975 – 8887) Volume 41– No. 20,.
  11. M. H. Chiang, Keunwoo Kim, Ching-Te Chaung and Tretz C, "High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices", Sep. 2006 IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2370–2377.
  12. D. Fried, J. S. Duster and K. T. Kornegay, "Improved Independent Gate N-Type FinFET Fabrication and Characterization," in IEEE Electron Device Letter, Vol. 24, No. 9, September 2003, pp. 593.
  13. M. Masahara et al. , "Demonstration of asymmetric gate-oxide thickness four terminal FinFETs having flexible threshold voltage and good subthreshold slope," 2007 IEEE Electron Device Letters, vol. 28, no. 3, pp. 217–219.
  14. A. Muttreja, P. Mishra, and N. K. Jha, "Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects," Jan. 2008, in Proc. Int. Conf. VLSI Design.
  15. V. Raj Kumar and A. Alfred kirubaraj, "Submicron 70nm CMOS Logic Design With FINFETs", International Journal of Engineering Science and Technology Vol. 2(9), 2010, 4751-4758.
  16. S. A. Tawfik, V. Kursun, Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic, in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, December 2008, pp. 1720–1723.
  17. S. A. Tawfik, V. Kursun, High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise, in: Proceedings of the IEEE International Conference on Microelectronics, December 2007, pp. 175–178.
  18. D. Fried, J. S. Duster and K. T. Kornegay, "Improved Independent Gate N-Type FinFET Fabrication and Characterization," in IEEE Electron Device Letter, Vol. 24, No. 9, September 2003, pp. 593.
  19. S. O'uchi, K. Sakamoto, K. Endo, M. Masahara, T. Matsukawa, Y. X. Liu, M. Hioki, T. Nakagawa, T. Sekigawa, H. Koike and E. Suzuki, "Variable-Threshold-Voltage FinFETs with a Control-Voltage Range with in the Logic-Level Swing Using Asymmetric Work-Function Double Gates," 2008 in VLSI Technology, Systems and Applications,.
  20. D. M. Fried, E. J. Nowak, J. Kedzierski, J. S. Duster,and K. T. Kornegay. A fin-type independent double-gate NFET June 2003 In Proc. Device Research Conf. , pages 45–46.
  21. H. Mahmoodi, S. Mukhopadhyay, and K. Roy. High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs. Oct. 2004 In Proc. IEEE Int. SOI Conf. , pages 67–68.
  22. W. Zhang, J. G. Fossum, L. Mathew, and Y. Du. Physical insights regarding design and performance of independent-gate FinFETs. Oct. 2005 IEEE Electronic Device Lett. , 52(10):2189–2206.
Index Terms

Computer Science
Information Sciences

Keywords

Independent gate FinFET circuit High performance Short channel effects (SCEs) Multiple supply Threshold voltage Cadence virtuoso tool.

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