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Topology Re-Configuration for On-Chip Networks with Back-Tracking
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 79 - Number 17 |
| Year of Publication: 2013 |
| Authors: M. Venkata Theertha, Rajesh Nandi, B. V. S. L. Bharathi |
10.5120/13965-1939
|
M. Venkata Theertha, Rajesh Nandi, B. V. S. L. Bharathi . Topology Re-Configuration for On-Chip Networks with Back-Tracking. International Journal of Computer Applications. 79, 17 ( October 2013), 40-45. DOI=10.5120/13965-1939
Abstract
Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex multi-core system-on-chip or chip multiprocessor. In this paper, a novel reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented with backtracking which provides guaranteed throughput is presented. The proposed NoC supports multiple applications by configuring its topology to the topology which matches the input application and also supports a dead-and-live lock free dynamic path set-up scheme. The re-configurability can be achieved by changing the inter-router connections to some predefined configuration corresponding to the application. This increases the support for higher number of applications which further increases the traffic congestion leading to path blockages and substantially to data loss. To manage the blockages and to support a dead and live lock free dynamic path set-up scheme we go for back-tracking. This can be achieved with an efficient and proper design of on-chip switching nodes. This paper first introduces the proposed reconfigurable topology and then deals with the back-tracking feature. Finally the architecture is valuated for power and area.
References
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