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Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic

by G. Mareswara Rao, S. Rajendar
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 80 - Number 15
Year of Publication: 2013
Authors: G. Mareswara Rao, S. Rajendar
10.5120/13935-1886

G. Mareswara Rao, S. Rajendar . Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic. International Journal of Computer Applications. 80, 15 ( October 2013), 9-12. DOI=10.5120/13935-1886

@article{ 10.5120/13935-1886,
author = { G. Mareswara Rao, S. Rajendar },
title = { Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic },
journal = { International Journal of Computer Applications },
issue_date = { October 2013 },
volume = { 80 },
number = { 15 },
month = { October },
year = { 2013 },
issn = { 0975-8887 },
pages = { 9-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume80/number15/13935-1886/ },
doi = { 10.5120/13935-1886 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:54:50.864805+05:30
%A G. Mareswara Rao
%A S. Rajendar
%T Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 80
%N 15
%P 9-12
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed design is compared with the conventional implicit type data close to output (ip-DCO) flip-flop. As compared to the conventional pulse triggered flip-flop, the proposed pulsed flip-flop (PFF) design features best speed, power and power-delay-product performance. The proposed technique is implemented using HSPICE CMOS 90nm technology. The average power consumption for 50% switching activity is reduced by 12. 75% as compared to conventional ip-DCO.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Low power pulsed flip-flop pass transistor logic critical path power-delay-product

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