CFP last date
20 May 2024
Reseach Article

Performance Estimation of n-bit Classified Adders

by Oday Abdul Lateef Abdul Ridha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 80 - Number 9
Year of Publication: 2013
Authors: Oday Abdul Lateef Abdul Ridha
10.5120/13888-1809

Oday Abdul Lateef Abdul Ridha . Performance Estimation of n-bit Classified Adders. International Journal of Computer Applications. 80, 9 ( October 2013), 11-15. DOI=10.5120/13888-1809

@article{ 10.5120/13888-1809,
author = { Oday Abdul Lateef Abdul Ridha },
title = { Performance Estimation of n-bit Classified Adders },
journal = { International Journal of Computer Applications },
issue_date = { October 2013 },
volume = { 80 },
number = { 9 },
month = { October },
year = { 2013 },
issn = { 0975-8887 },
pages = { 11-15 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume80/number9/13888-1809/ },
doi = { 10.5120/13888-1809 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:54:05.657779+05:30
%A Oday Abdul Lateef Abdul Ridha
%T Performance Estimation of n-bit Classified Adders
%J International Journal of Computer Applications
%@ 0975-8887
%V 80
%N 9
%P 11-15
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This work presents a performance estimation of classified n-bit binary adders. Since gate count and gate level depth directly related to speed, area, and power consumption of the adder circuit, therefore they are adopted as performance criteria. 2-inputs gate model is adopted as basic unit for the performance evaluation. The main focus of the work on carry ripple, carry lookahead, and multilevel carry select adders. The study showed that ripple carry adder is the best among other adders from area point of view. Whereas carry lookahead and multilevel carry select based on carry lookahead adders are the best from delay point of view. For the area delay product, 3 levels carry select adder based on carry ripple showed that it is the best.

References
  1. Olivieri, M. , Design of synchronous and asynchronous variable-latency pipelined multipliers. IEEE transaction on very large scale integration (VLSI) systems, Vol. 9: 256-262, 2004.
  2. R. UMA,Vidya Vijayan, M. Mohanapriya, Sharon Paul, Area, Delay and Power Comparison of Adder Topologies, International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 1, February 2012.
  3. Shailesh Siddha, Area Efficient 4-Input Decimal Adder Using CSA and CLA, Journal of Science and Technology, Vol. 3 No. 2, 2013
  4. R. Uma, 4-Bit Fast Adder Design: Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits, International journal of advanced engineering sciences and technologies, Vol. 7, No. 2, 2011.
  5. Deepa Sinha, Tripti Sharma, K. G. Sharma, B. P. Singh, Ultra Low Power 1-Bit Full Adder, International Symposium on Devices MEMS, Intelligent Systems & Communication (ISDMISC) 2011 Proceedings published by International Journal of Computer Applications® (IJCA)
  6. Pudi, V. and Sridharan, K. "Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA " , IEEE Transactions on Nanotechnology, Volume:11 , Issue: 1, 2012.
  7. Jian-Fei Jiang; Zhi-Gang Mao; Wei-Feng He; Qin Wang, "A New Full Adder Design for Tree Structured Arithmetic Circuits", 2nd International Conference on Computer Engineering and Technology(ICCET), Vol. 4, pp. 246-249,2010.
  8. SubodhWairya, Rajendra Kumar Nagaria, and Sudarshan Tiwari, Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design, VLSI Design, Hindawi Publishing Corporation, Volume 2012, Article ID 173079
  9. Shubin, V. V. , Analysis and comparison of ripple carry full adders by speed , International Conference and Seminar on Micro/NanoTechnologies and Electron Devices(EDM), pp. 132-135, 2010.
  10. Ahmet Sertba? and R. Selami özbey, A performance analysis of classified binary adder architectures and the vhdl simulations, Istanbul university-Journal of electrical & electronics engineering, vol. 4, no. 1, 2004
  11. Morris Mano, Michael D. Ciletti, Digital Design With an Introduction to the Verilog HDL, Pearson Education, Inc, fifth edition, 2013.
  12. Stephen Brown and Zvonko Vranesic, Fundamentals of digital logic with VHDL design, McGraw Hill, third edition, 2009.
  13. M. Rajesh, R. Manikandan, Efficient Implementation of Carry Free Select Adder, Journal of Science and Technology ,Vol. 3, No. 2, 2013.
  14. Padma Devi, Ashima Girdher, Balwinder Singh, Improved Carry Select Adder with Reduced Area and LowPower Consumption, International Journal of Computer Applications, Vol. 3, No. 4, 2010.
Index Terms

Computer Science
Information Sciences

Keywords

Performance estimation gate level depth gate count delay area power consumption ripple adder carry ahead adder multilevel carry select adder.