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Design of High Speed Modulo 2n+1 Adder

by M. Varun, M. Nagarjuna, M. Vasavi
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 81 - Number 17
Year of Publication: 2013
Authors: M. Varun, M. Nagarjuna, M. Vasavi
10.5120/14213-2110

M. Varun, M. Nagarjuna, M. Vasavi . Design of High Speed Modulo 2n+1 Adder. International Journal of Computer Applications. 81, 17 ( November 2013), 5-11. DOI=10.5120/14213-2110

@article{ 10.5120/14213-2110,
author = { M. Varun, M. Nagarjuna, M. Vasavi },
title = { Design of High Speed Modulo 2n+1 Adder },
journal = { International Journal of Computer Applications },
issue_date = { November 2013 },
volume = { 81 },
number = { 17 },
month = { November },
year = { 2013 },
issn = { 0975-8887 },
pages = { 5-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume81/number17/14213-2110/ },
doi = { 10.5120/14213-2110 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:56:17.446619+05:30
%A M. Varun
%A M. Nagarjuna
%A M. Vasavi
%T Design of High Speed Modulo 2n+1 Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 81
%N 17
%P 5-11
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The two different architectures for adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of modulo 2n+1 addition. This sparse approach is enabled by the introduction of inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adder can be implemented in a smaller area and consume less power compared to all earlier proposals, maintaining a high operation speed. The second adder architecture unifies the design of modulo 2n+1 adder. Both the adders are derived and compared by using the simulation results.

References
  1. R. Chokshi, K. S. Berezowski, A. Shrivastava, and S. J. Piestrak, "Exploiting Residue Number System for Power-Efficient Digital Signal Processing in Embedded Processors," Proc. Int'l Conf. Compilers, Architecture, and Synthesis for Embedded Systems (CASES '09), pp. 19-28, 2009.
  2. L. M. Leibowitz, "A Simplified Binary Arithmetic for the Fermat Number Transform," IEEE Trans. Acoustics, Speech and Signal Processing, vol. ASSP-24, no. 5, pp. 356-359, Oct. 1976.
  3. G. Jaberipur and B. Parhami, "Unified Approach to the Design of Modulo-(2n ± 1) Adders Based on Signed-LSB Representation of Residues," Proc. 19th IEEE Symp. Computer Arithmetic, pp. 57-64, 2009.
  4. J. J. Shedletsky, "Comment on the Sequential and Indeterminate Behavior of an End-Around-Carry Adder," IEEE Trans. Computers, vol. C-26, no. 3, pp. 271-272, Mar. 1977.
  5. R. Zimmermann, "Binary Adder Architectures for Cell-Based VLSI and Their Synthesis," PhD dissertation, Swiss Fed. Inst. Of Technology, 1997.
  6. R. Zimmerman, "Efficient VLSI Implementation of Modulo 2n±1 Addition and Multiplication," Proc. 14th IEEE Symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
  7. H. T. Vergos, C. Efstathiou, and D. Nikolos, "Diminished-One Modulo 2n + 1 Adder Design," IEEE Trans. Computers, vol. 51, no. 12, pp. 1389-1399, Dec. 2002.
  8. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Modulo 2n ± 1 Adder Design Using Select Prefix Blocks," IEEE Trans. Computers, vol. 52, no. 11, pp. 1399-1406, Nov. 2003.
  9. S. -H. Lin and M. -H. Sheu, "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection," IEEE Trans. Circuits and Systems II, vol. 55, no. 9, pp. 897-901, Sept. 2008.
  10. G. Dimitrakopoulos and D. Nikolos, "High-Speed Parallel-Prefix VLSI Ling Adders," IEEE Trans. Computers, vol. 54, no. 2, pp. 225- 231, Feb. 2005.
  11. H. T. Vergos and C. Efstathiou, "Efficient Modulo 2n + 1 Adder Architectures," Integration, the VLSI J. , vol. 42, no. 2, pp. 149-157, Feb. 2009.
  12. M. Bayoumi, G. Jullien, and W. Miller, "A VLSI Implementation of Residue Adders," IEEE Trans. Circuits and Systems, vol. CAS-34, no. 3, pp. 284-288, Mar. 1987.
  13. A. Hiasat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Trans. Computers, vol. 51, no. 1, pp. 84-89, Jan. 2002.
  14. C. Efstathiou, H. T. Vergos, and D. Nikolos, "Fast Parallel-Prefix Modulo 2n + 1 Adders," IEEE Trans. Computers, vol. 53, no. 9, pp. 1211-1216, Sept. 2004.
  15. H. T. Vergos and C. Efstathiou, "A Unifying Approach for Weighted and Diminished-1 Modulo 2n + 1 Addition," IEEE Trans. Circuits and Systems II, vol. 55, no. 10, pp. 1041-1045, Oct. 2008.
  16. R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. C-31, no. 3, pp. 260-264, Mar. 1982.
  17. S. Mathew, M. Anders, R. K. Krishnamurthy, and S. Borkar, "A 4- GHz 130-nm Address Generation Unit with 32-bit Sparse-Tree Adder Core," J. Solid-State Circuits, vol. 38, no. 5, pp. 689-695, May 2003.
  18. Haridimos T. Vergos and Giorgos Dimitrakopoulos, "On Modulo 2n + 1 adder design", IEEE transactions on computers, vol. 61, No. 2, Feb, 2012.
  19. K. Nehru, A. Shanmugam and S. Vadivel, "Design of 64-Bit Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits".
Index Terms

Computer Science
Information Sciences

Keywords

IEAC adder Sparse-4 adder RNS

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