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Reseach Article

Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits

by Sk. Mahammad Akram, V. Leela Rani, K. Sailaja
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 82 - Number 18
Year of Publication: 2013
Authors: Sk. Mahammad Akram, V. Leela Rani, K. Sailaja
10.5120/14265-2411

Sk. Mahammad Akram, V. Leela Rani, K. Sailaja . Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits. International Journal of Computer Applications. 82, 18 ( November 2013), 24-28. DOI=10.5120/14265-2411

@article{ 10.5120/14265-2411,
author = { Sk. Mahammad Akram, V. Leela Rani, K. Sailaja },
title = { Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits },
journal = { International Journal of Computer Applications },
issue_date = { November 2013 },
volume = { 82 },
number = { 18 },
month = { November },
year = { 2013 },
issn = { 0975-8887 },
pages = { 24-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume82/number18/14265-2411/ },
doi = { 10.5120/14265-2411 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:58:06.346899+05:30
%A Sk. Mahammad Akram
%A V. Leela Rani
%A K. Sailaja
%T Implementation of Low Leakage and High Performance 8-Bit ALU for Low Power Digital Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 82
%N 18
%P 24-28
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The insist for portable devices is fulfilled by the growing CMOS technology. As the size of the transistor shrinks, the leakage power component augments exponentially. Thus it becomes a critical metric for the future technologies. This paper deals with the techniques like GATED VDD, AVLS, AVLG, and AVL for reducing leakage power. These techniques are implemented on 8-bit ALU. 80% of cutback in leakage power can be achieved by applying proposed technique with minimum delay and area overhead. The circuit is simulated on cadence(R) Virtuoso(R) in 90 nanometer CMOS technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

8-bitALU Gated -Vdd AVLS AVLG and AVL