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Hardware Implementation of High Speed RC4 Algorithm in FPGA

by Chandra Mouli. R, K. R. K. Sastry
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 83 - Number 4
Year of Publication: 2013
Authors: Chandra Mouli. R, K. R. K. Sastry
10.5120/14437-2589

Chandra Mouli. R, K. R. K. Sastry . Hardware Implementation of High Speed RC4 Algorithm in FPGA. International Journal of Computer Applications. 83, 4 ( December 2013), 21-22. DOI=10.5120/14437-2589

@article{ 10.5120/14437-2589,
author = { Chandra Mouli. R, K. R. K. Sastry },
title = { Hardware Implementation of High Speed RC4 Algorithm in FPGA },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 83 },
number = { 4 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 21-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume83/number4/14437-2589/ },
doi = { 10.5120/14437-2589 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:58:30.765865+05:30
%A Chandra Mouli. R
%A K. R. K. Sastry
%T Hardware Implementation of High Speed RC4 Algorithm in FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 83
%N 4
%P 21-22
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents high speed and an area efficient hardware implementation of the RC4 algorithm. The proposed design uses Block RAM (BRAM) implementation to reduce the area and to increase the speed of operation hence throughput. The proposed design uses only one 256 bytes simple dual port RAM for key stream generation and it takes 3 clock cycles per byte. It supports a variable key length of from 1 byte to 256 bytes and achieves 54. 8MB/s throughput at 164. 6MHz operating frequency. The design is targeted on XC2V250FG256 Xilinx FPGA and met the operating frequency of 164. 6MHz. The RC4 algorithm is implemented in Verilog HDL.

References
  1. P. Hamalainen, M. Hannikainen, T. Hamalainen and J. Saarinen, "Hardware Implementation of the Improved WEP and RC4 Encryption Algorithms for Wireless Terminals", The European Signal Processing Conference (EUSIPCO'2000), pp. 2289-2292, September 5-8, 2000.
  2. B. Schneier, D. Whiting, "Fast Software Encryption: Designing Encryption Algorithms for Optimal Software Speed on the Intel Pentium Processor", Fast Software Encryption workshop (FSE97), LNCS, Vol. 1267, pp. 242-259, Springer-Verlag, Haifa, Israel, January 20-22, 1997.
  3. P. D. Kundarewich, S. J. E. Wilton, A. J. Hu, "A CPLD-Based RC-4 Cracking System", The 1999 Canadian Conference on Electrical and Computer Engineering, May 1999, vol. 1, pp. 397 – 402.
  4. P. Kitsos, G. Kostopoulos, N. Sklavos, and O. Koufopavlou, "Hardware Implementation of the RC4 stream Cipher", IEEE 46th Midwest Symposium on Circuits & Systems, vol. 3, pp. 1363-1366, 2003.
  5. K. H Tsoi, K. H Lee and P. H. W Leong, "A Massively Parallel RC4 Key Search Engine", Proc. of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'02), September 22 - 24, 2002 Napa, California, pp. 13-21.
  6. S. S. Gupta, K. Sinha, S. Maitra and B. P. Sinha, "One Byte per Clock: A Novel RC4 Hardware", 11th International Conference on Cryptology - Indocrypt 2010 Dec. 2010, India.
  7. William Stallings, "Cryptography and Network Security–Principles and Practice", Fifth Edition, Prentice Hall, 2011.
Index Terms

Computer Science
Information Sciences

Keywords

BRAM CPLD FPGA RC4 Algorithm Stream Cipher Simple Dual Port RAM.

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